• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6C
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• pp.594-601
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• 2003

High-speed WLAN(Wireless Local Area Network) systems operating in 5GHz band use OFDM transmission technique. OFDM technique transmits data in parallel and has many advantage compared with the serial transmission system-for example, robustness to time variance of channel. OFDM technique use the orthogonal multicarriers. The ICI(InterChannel Interference) caused by the orthogonality destruction between subcarriers. hamper the BER performance. In this paper, we propose the synchronization techniques for high-speed WLAN system designed to support user data rates up to 54Mbps at 5GHz. The proposed synchronization techniques are the reduced complexity structure having the similar performance compared with the conventional synchronization techniques.

• Transactions of the Korean Society of Automotive Engineers
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• v.9 no.6
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• pp.143-151
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• 2001

During the past several years, the major interests of car manufacturers in development of automatic transmission were in durability and shift quality. However, a large number of researches for improving shift quality that are based on dynamic characteristics of shifting mechanism have been rarely adopted in the developing process because it is quite difficult to predict the shifting performance from the dynamics simulation. One of the important reasons for the difference between simulation results and experiments arises from the automatic transmission hydraulic system that consists of many valves with high order model and shows a lot different dynamics to temperature variation. In this work, hardware-in-the-loop simulation system for automatic transmission was developed f3r improving the accuracy of simulated result by combining the real-time simulation model with the real hydraulic system. The real-time simulation for automatic transmission model excluding hydraulic system is executed with TI's TMS320C31 DSP and the interfacing board which includes 12bit A/D, PWM signal generator and driver, serial driver ,etc is designed for acquiring the simulation data and signal interface with hydraulic system. We verified the proper operation and correctness of shifting result by comparing the off-line simulation result with that of HILS and experimental result which was performed on transmission dynamometer driven by electric motor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

• Proceedings of the KOSOMBE Conference
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• v.1996 no.05
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• pp.179-183
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• 1996

Most of the conventional electrocardiogaphies fail to detect signals other than P-QRS-T due to the limited SNR and bandwidth. High-resolution electrocardiography (HRECG) provides better SNR and wider bandwidth for the detection of micro-potentials with higher frequency components such as ventricual late potentials(LP). In this paper, we developed a HRECG using uncorrected XYZ lead. The overall gain of the amplifier is 4000 and the bandwidth is $0.5{\sim}300Hz$ without using 60Hz notch filter. Three 16-bit AH converters sample X, Y, and Z signals simultaneously with a sampling frequency of 2000Hz. Sampled data are transmitted to PC via a DMA-controlled serial communication channel using RS-485 and HDLC protocol. The noise level of the developed HRECG is less than $5{\mu}V_{rms,\;RTI}$. In order to further reduce the noise level, signal averaging technique is implemented utilizing template matching method. The SNR of the developed HRECG is high enough for the detection of LP.

• Journal of Distribution Research
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• v.1 no.1
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• pp.83-107
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• 1996

The concern of external environment is growing up in the field of channel distribution. In the former channel distribution, the channel distribution environment is little bit unmoveable owing to a powerful manufacture control against poor distributor. Therefore intra-efficiency is channel member's core interest. The structure of channel governance, however, come to be changable because of the mature distributor power against manufacturer such as a Price Break, JIT of channel governance, and a serial of change. Accordingly, it is acceptable that the interest of external-environment of channel members' is more and more enlarged, and external-environment change in the channel distribution make the serious problems in intraorganizational system. Thus, it is meaningful that this study try to discover the consumer power as external environment factor and to find the best strategy to overcome this consumer power. Resource dependence theory, Transaction cost theory, Political Economic Approach, and Working partnership Approach are the theory foundation of the reasearch. Apparel franchise is a sample to analyse the hypothesis and correlation and multi-regression are a chief tools to estimate the hypothesis. Thus, the above results imply that a flexible governance is appropriate to consumer power, conflict is not intervening value between consumer power and channel governance, and the channel member's satisfaction can be confirmed in the flexible governance better than control governance.

• The Journal of the Acoustical Society of Korea
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• v.26 no.6
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• pp.269-275
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• 2007

Pervasive Multi-channel audio systems are being realized due to advances in digital technology. This paper proposes an efficient system that serially connects individual speakers with bidirectional digital communication capability by means of SoC design. In particular, each speaker can identify the bit stream assigned to the speaker and convert it into analog audio. Furthermore, the speaker can self-diagnose the speaker functionality by utilizing the designed capability to measure frequencies of various square wave test signals. The proposed system running on 200MHz clock yielded restoration of analog output signal with latency of only $500{\mu}s$ compared to directly driving the speakers in a traditional way.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.