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http://dx.doi.org/10.7840/kics.2013.38C.2.196

Design of High Speed LDPC Encoder Based on DVB-S2 Standard  

Park, Gun Yeol (한국해양대학교 전파공학과)
Lee, Seong Ro (목포대학교 정보전자공학과)
Jeon, Sung Min (목포대학교 정보전자공학과)
Jung, Ji-Won (한국해양대학교 전파공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.38C, no.2, 2013 , pp. 196-201 More about this Journal
Abstract
In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.
Keywords
DVB-S2; Low Density Parity Check; CNU(Check Node Update); BNU(Bit Node Update);
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