• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.314-317
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• 2012

최근 차량의 멀티미디어 장치들이 증가하면서 이 장치들을 광 네트워크로 연결하여 멀티미디어 데이터를 송 수신해서 사용할 수 있는 MOST(Media Oriented Systems Transport) 네트워크를 적용한 차량들이 늘어나고 있다. MOST 네트워크는 최근 자동차 멀티미디어 시스템에 넓게 사용되고 있는 통신 시스템으로서, 동기 및 비동기 데이터를 동시에 전송할 수 있고, 최근에는 150Mbps를 전송할 수 있는 MOST150 네트워크를 이용한 연구가 활발히 진행되고 있다. 본 논문에서는 MOST150 네트워크에서 Audio 데이터 입출력을 제어하기 위한 알고리즘을 설계 및 구현하였다. Audio 데이터를 제어하는 방식은 ADC(Analog to Digital Converter)를 통해 Audio 데이터가 들어오면 IOC(IO Companion)를 통해 INIC으로 Audio데이터를 전달한다. INIC은 MOST150 네트워크로 데이터를 전송하고 그렇게 보내진 Audio 데이터를 MOST150 네트워크 내부의 다른 장치에서 INIC을 통해 데이터를 수신하여 DAC(Digital to Analog Converter)를 통해 Audio 장치에서 소리가 나는 것을 테스트하여 정상적으로 동작함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.608-614
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• 2015

A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.157-160
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• 2002

This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.484-485
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• 2018

DAC 는 디지털-아날로그 변환 회로는 디지털 전기 신호를 아날로그 전기 신호로 변환하는 전자 회로이다. 특히 최근 음성 신호는 그 효율성 및 경제성 때문에 디지털 데이터 형태로 저장/전송되고 있어 DAC 는 음성 관련 사업에서 필수적으로 쓰이고 있다. 본 논문은 음성 신호의 디지털-아날로그 변환 시 DAC 의 성능에 대한 분석 및 시험 결과를 소개한다.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.11-21
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• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.