• Proceedings of the KIEE Conference
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• 1997.07a
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• pp.234-237
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• 1997

In the Closing time in order to operate synchronous generators parallely, it is generated the asynchronous phenomena. These asynchronous phenomena give rise of the eddy current on the rotor. These eddy current are solved analytically for the Laplace' Equ. ${\nabla}^2{\widetilde{H}}=0$ in free space and for the Bullard's Equ. ${\nabla}^2{\widetilde{H}}$+${\sigma}_r{\mu}_r{\nabla}$${\times}$${\widetilde{\nu}}_r$${\times}$${\widetilde{H}}^{III}$=${\sigma}_r{\mu}_r{\frac{{\partial}H}{{\partial}t}}$ for the rotor by using each double Fourier series component of the 3D H-field

• ETRI Journal
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• v.35 no.4
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• pp.710-713
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• 2013

We propose a new space-time block coding (STBC) for asynchronous cooperative systems in full-duplex mode. The orthogonal frequency division multiplexing (OFDM) transmission technique is used to combat the timing errors from the relay nodes. At the relay nodes, only one OFDM time slot is required to delay for a pair-wise symbol swap operation. The decoding complexity is lower for this new STBC than for the traditional quasi-orthogonal STBC. Simulation results show that the proposed scheme achieves excellent performances.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.103-109
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• 2016

Corrective control for asynchronous sequential machines is a novel automatic control theory that compensates illegal behavior or adverse effects of faults in the operation of existent asynchronous machines. In this paper, we propose a scheme of diagnosing and tolerating faults occurring to input channels of corrective control systems. The corrective controller can detect faults occurring in the input channel to the controlled machine, whereas those faults happening in the external input channel cannot be detected. The proposed scheme involves an outer operator which, upon receiving the state feedback, diagnoses a fault and sends an appropriate command signal to the controller for tolerating faults in the external input channel.

• Journal of the Korean Society of Safety
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• v.12 no.3
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• pp.67-75
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• 1997

This paper presents a study on the application of Asynchronous Team(A-Team) theory for QVC(Reactive power control) and security assessment in a power system. Reactive power control problem is the one of optimally establishing voltage level given reactive power sources, which is very important problem to supply the demand without interruption and needs methods to alleviate a bus voltage limit violation more quickly. It can be formulated as a mixed-integer linear programming(MILP) problem without deteriorating of solution accuracy to a certain extent. The security assessment is to estimate the relative robustness of the system and deterministic approach based on AC load flow calculations is adopted to assess it, especially voltage security. A distance measure, as a measurement for voltage security, is introduced. In order to analyze the above two problem, reactive power control and static security assessment, In an integrated fashion, a new organizational structure, called an A-team, is adopted. An A-team is well-suited to the development of computer-based, multi-agent systems for operation of large-scaled power systems. In order to verify the usefulness of the suggested scheme herein, modified IEEE 30 bus system is employed as a sample system. The results of a case study are also presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.173-181
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• 2014

This paper addresses the problem of model matching control for a class of systems modeled as input/output asynchronous sequential machines. Based on the feedback control scheme, we design a corrective controller that compensates the behavior of the closed-loop system so as to match a reference model. Whereas the former studies use state observers and the output burst for designing a controller, the present research needs neither the observer nor the output burst in controller design. We define the 'output equivalent machine' of the considered machine to describe the existence condition and the construction algorithm for the proposed controller. A case study is provided to show the operation of the proposed corrective controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.11
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• pp.2056-2063
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• 2011

A time based software simulator for the PRT system operation is presented. The purpose of the simulator is to estimate the passenger transportation performance of the PRT system. In this paper, it is presented how the system is modeled in the simulator to estimate passenger transportation performance and the running algorithm of the modeled subsystem. An application sample is also presented to find the system's design parameter to satisfy the transportation needs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design