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A Design Method of a Completion Signal Generation Circuit of Memory for Asynchronous System  

서준영 (충북대학교 정보통신공학과, 컴퓨터정보통신연구소)
이제훈 (충북대학교 정보통신공학과, 컴퓨터정보통신연구소)
조경록 (충북대학교 정보통신공학과 컴퓨터정보통신연구소)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.10, 2004 , pp. 105-113 More about this Journal
Abstract
This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.
Keywords
Asynchronous memory; Self-Timed; Completion signal; Delay-insensitive;
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