• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.724-733
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• 2003

Generally, dividers have been designed to use iteration, but recently the research on the pipelined divider is underway. It is a difficult point in the known pipelined division unit that a large lookup table is required. In this paper, the cost-effective pipelined divider is proposed, that needs a lookup table smaller than that of the other pipelined divider. The latency of the proposed divider is 3 cycles. We obtain a 30% reduced area than that of P. Hung.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of Preventive Medicine and Public Health
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• v.19 no.1 s.19
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• pp.130-136
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• 1986

The particle size of suspended particulates was measured by a Anderson air sampler from Mar. 1982 to Feb. 1984 in a part of Seoul. It was concluded as follows : 1) The arithmetic concentration of suspended particulates was $147.8{\mu}g/m^3$ in Spring, 136.9 in Summer, 131.9 in Autumn and 158.1 in Winter respectively. 2) The cumulative distribution of suspended particulates size in logarithmic diagram showed similar to normal log distribution. 3) The atmospheric particulate matters showed a bimodal size distribution on the base of unit particle concentrations, which divided at approximately $2{\mu}m$ in the diameter. 4) While the fine particulates less than $2.1{\mu}m\;was\;35.4{\sim}45.0%$, the coarse particulates was $55.0{\sim}64.5%$. 5) The higher the concentration of suspended particulates, the more increased the ratio of fine particulates. The higher the concentration of suspended particulates, the lower median size of suspended particulate as well. 6) The respirable dust particulates less than $4.7{\mu}m\;was\;52.2{\sim}62.9%$ in seasonal average through the 2 year samples. With the above result, air pollution concerned with public health could be evaluated and the control measures also are suggested.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• Journal of The Korean Association of Information Education
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• v.13 no.3
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• pp.325-339
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• 2009

Many current researches are limited in the statistics field, which is a part of mathematics class in the secondary school. Moreover, it's hard to apply to the elementary school since they are written in English. To overcome this limitations, the objectives from the unit that is suitable for using EXCEL in the elementary mathematics lessons are selected in this research. And a problem-based learning model for these lessons would be introduced that it can help students to focus on solving substances of the problems by reducing the time for arithmetic calculation.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.415-418
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• 2008

Some embedded microprocessors do not have an FPU(Floating Point Unit) due to a circuit complexity and power consumption. The performance speed of MPEG-4 AAC decoder on this hardware environment would be slower than corresponding speed for playing back of the decoded results. Therefore, irritating and high-pitched noises are interleaved in the original the audio data. So, in order to play MPEG-4 AAC file on such PDA, a new algorithm that transforms floating-point arithmetic to one with integers, is needed. We have developed a transformation algorithm from floating-point operation to integer operation and implemented the PDA's AAC Player. We also show the efficiency of our proposed method with the experimental results.

• Kyungpook Mathematical Journal
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• v.28 no.2
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• pp.129-139
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• 1988

Let $T^{\alpha}_{\lambda}$(p, A, B) denote the class of functions $$f(z)=z^p-{\sum\limits^{\infty}_{k=1}}{\mid}a_{p+k}{\mid}z^{p+k}$$ which are regular and p valent in the unit disc U = {z: |z| <1} and satisfying the condition $\left|{\frac{{e^{ia}}\{{\frac{f^{\prime}(z)}{z^{p-1}}-p}\}}{(A-B){\lambda}p{\cos}{\alpha}-Be^{i{\alpha}}\{\frac{f^{\prime}(z)}{z^{p-1}}-p\}}}\right|$<1, $z{\in}U$, where 0<${\lambda}{\leq}1$, $-\frac{\pi}{2}$<${\alpha}$<$\frac{\pi}{2}$, $-1{\leq}A$<$B{\leq}1$, 0<$B{\leq}1$ and $p{\in}N=\{1,2,3,{\cdots}\}$. In this paper, we obtain sharp results concerning coefficient estimates, distortion theorem and radius of convexity for the class $T^{\alpha}_{\lambda}$(p, A, B). It is further shown that the class $T^{\alpha}_{\lambda}$(p, A, B) is closed under "arithmetic mean" and "convex linear combinations". We also obtain class preserving integral operators of the form $F(z)=\frac{p+c}{z^c}{\int^z_0t^{c-1}}f(t)dt$, c>-p, for the class $T^{\alpha}_{\lambda}$(p, A, B). Conversely when $F(z){\in}T^{\alpha}_{\lambda}$(p, A, B), radius of p valence of f(z) has also determined.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.