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A Study On the Design of a Floating Point Unit for MPEG-2 AAC Decoder  

구대성 (조선대학교 전자공학과)
김필중 (성화대학 인터넷정보계열)
김종빈 (성화대학 인터넷정보계열)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TE / v.39, no.4, 2002 , pp. 355-355 More about this Journal
Abstract
In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.
Keywords
MPEG-2 AAC; ISO/IEC 13818-7; FPU; Radix-4 Booth Algorithm;
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  • Reference
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