• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.225-228
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• 2002

The adhesion effect between the oxide layer and the metal layer has been studied by RTP anneal. Two types of oxides, BPSG and P-TEOS, were used as a bottom layer under multi-layered metal film. We observe the interface between oxide and metal layer using SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy). Adhesion failure was occurred by interfacial reaction between the BPSG oxide and the multi-layered metal film at 650"C RTP anneal. The phosphorus rich layer was observed at interface between BPSG oxide and metal layer by AES and TEM measurements. On the other hand adhesion was a)ways good in the sample used P-TEOS oxide as a bottom layer. We have known that adhesion between BPSG and multi-layered metal film was improved when the sample was annealed below $650^{\circ}C$.TEX>.

• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.280-285
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• 2003

The influence of silicon surface damage on nickel-silicide (NiSi) has been characterized and H$_2$ anneal and TiN rapping has been applied to suppress the electrical, morphological deterioration phenomenon incurred by the surface damage. The substrate surface is intentionally damaged using Ar IBE (Ion beam etching) which can Precisely control the etch depth. The sheet resistance of NiSi increased about 18% by the surface damage, which is proven to be mainly due to the reduced silicide thickness. It is shown that simultaneous application of H: anneal and TiN capping layer is highly effective in suppressing the surface damage effect.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.529-532
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• 1997

We studied the crystallization of a-Si:H thin film. Multi-crystallized Si films are preferred in many applications such as FPD, solar cells, RAM, and integrated circuits. Because most of these applications require a low temperature process, we investigated a crystallization of a-Si:H using a Cd layer. A metal Cd shows an eutectic point at a temperature of 321$^{\circ}C$. This paper present Cd layer assisted crystallization of a-Si:H film for the various grain growth Parameters such as anneal temperature, Cd layer thickness, and anneal time

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 추계 학술발표 강연 및 논문 개요집
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• pp.28-28
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• 1994

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2001년도 춘계학술발표회 초록집
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• pp.70-71
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• 2001

• 한국진공학회지
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• 제17권3호
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• pp.199-203
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• 2008

$O_2$ 플라즈마를 이용한 표면처리 공정이 Bio-FET (biologically sensitive field-effect transistor)에 미치는 영향을 조사하기 위하여, SOI (Silicon-on-Insulator) wafer와 sSOI (strained- Si-on-Insulator) wafer를 이용하여 pseudo-MOSFET을 제작하고 $O_2$ 플라즈마를 이용하여 표면처리를 진행하였다. 제작된 시료들은 back gated metal contact junction 방식으로 측정되었다. $I_D-V_G$ 특성과 field effect mobility 특성의 관찰을 통하여 $O_2$ 플라즈마 표면처리에 따른 각 시료들의 전기적 특성 변화에 대하여 관찰하였다. 그리고 $O_2$ 플라즈마 표면처리 과정에서 플라즈마에 의한 손상을 받은 시료들은 2% 수소희석가스 ($H_2/N_2$)를 이용한 후속 열처리 공정을 진행한 후 전기적 특성이 향상되는 것을 관찰할 수 있었다. 이는 수소희석가스를 이용한 후속 열처리 공정을 통하여 산화막과 Si 사이의 계면 준위와 산화막 내부의 전하 포획 준위를 감소시켰기 때문이다.

• Transactions on Electrical and Electronic Materials
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• 제1권4호
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• pp.1-6
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• 2000

The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

• 한국재료학회지
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• 제11권2호
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• pp.151-154
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• 2001

상부전극, Pt, Ir, 그리고 $IrO_2$, 에 따라 수소 열처리전과 후, 그리고 회복열처리시 누설전류특성을 고찰하였다. Pt/PLZT/Pt 케페시터는 수소열처리 후에 다시 회복열처리를 수행하면 완전히 이력곡선의 회복을 보이며 또한 피로특성도 거의 회복 된다. Pt과 IrO$_2$ 상부전극의 경우의 진 누설전류 특성은 열처리조건에 관계없이 강한 시간 의존성을 갖는 space-charge influenced injection모델에 적합하다. 반면에 Ir 상부전극의 경우는 Ir과 PLZT 사이의 계면에 헝성된 전도성 상인 $IrO_2$로 인해 높은 누설전류 밀도를 보이면서 relaxation current 영역이 없이 steady state 영역을 보이는, 주로 Schottky barrier 모델에 의해 설명된다.

• 한국전자현미경학회:학술대회논문집
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• 한국현미경학회 1994년도 제25회 학술대회 연제 초록
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• pp.23-23
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• 1994