• Title/Summary/Keyword: analog-to-digital conversion

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The Development of Industrial Communication Monitoring Board using AVR (AVR을 이용한 산업용 통신 모니터링 보드 개발)

  • Eum, Sang-hee;Lee, Byong-Hoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.6
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    • pp.1177-1182
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    • 2016
  • The most industrial instruments for monitoring and control are occurring the extension problem and the external protocol compatibility. In this paper, we developed the boards for the industrial communication monitoring that are able to convert the protocol in various communication between devices and instruments. These are consisted the main board and several sub-board. They can have extension using the main board connection. The sub-board support the each communication method or data transfer. The main board was used the Atmega 2560 Microprocessor of AVR series, and the sub-boards are have the Atmega 256 or Atmega 128 in the AVR series. We have designed to connect the sub-board using placed the 4 RS485 serial slots in the main board. The sub-boards were developed to support the analog and digital I/O. These are able to have monitoring by CAN and Ethernet communication. The experimental results, we obtained good data transfer rate and conversion rate.

Asynchronous IR-UWB ranging system (비동기 IR-UWB 레인징 시스템)

  • Choi, You-Shin;Yang, Hoon-Gee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.587-594
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    • 2010
  • In this paper, we propose an asynchronous IR-UWB ranging system based on the two-way ranging protocol. The periodic pulse sequence is used to measure a distance between two devices. At the receiver, a received signal is first transformed into a frequency-domain signal using an analog correlator bank and digital signal processing is followed in the frequency-domain. This make it possible for the system to use an ADC with a conversion speed of pulse rate. The proposed algorithm at the receiver side includes a peak detection procedure using mutipath channel compensation and matched filtering, and retransmits a pulse sequence synchronized with the detected peak. The validity of the proposed algorithm is verified from simulation results where the CM1 channel is assumed.

A Study on Optimal Hydrophone Arrangement for The Direction Finding of High Speed Moving Target in Underwater (수중에서 고속 기동하는 표적의 방위 탐지를 위한 최적의 청음기 배치 연구)

  • Han, Min-Su;Choi, Jae-Yong;Kang, Dong-Seok;Son, Kweon;Lee, Phil-ho
    • Journal of the Korea Institute of Military Science and Technology
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    • v.20 no.3
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    • pp.369-375
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    • 2017
  • One of good DF(Direction Finding) methods is based on TDOA(Time Difference of Arrival) estimation when finding underwater moving target. For small DF error, high time resolution A/D(Analog-to-digital) conversion board and long baseline are needed. But the result of sea trial about close-range and high speed moving target, spatial correlation coefficient and appeared poor properties below 0.3 when hydrophone arrangement are separated over 6 ${\lambda}$ because of underwater fading channel. And we also find out that the distance between hydrophone should be under 4 ${\lambda}$ apart to take advantage of spatial correlation coefficient gain and performance of DF in underwater moving channel environments.

Development of Switched-Capacitor Sigma-Delta Modulator for Automotive Radars (차량 레이더용 스위치 커패시터 시그마-델타 변조기 개발)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1887-1894
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    • 2010
  • This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

A Multiple-Symbol Interval Estimation Algorithm for Precision Improvement of Initial Carrier-Frequency Synchronization in Multiband-OFDM UWB System (MB-OFDM UWB 시스템에서 초기 반송파 주파수 동기의 정확도 향상을 위한 다중 심볼 간격 추정 알고리즘)

  • Jin, Yong-Sun;Park, Kye-Wan
    • 전자공학회논문지 IE
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    • v.47 no.3
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    • pp.35-40
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    • 2010
  • In this paper, we propose an algorithm to improve the precision of initial carrier-frequency offset estimation for multiband-OFDM (MB-OFDM) UWB system which is considering the quantization-noise effect. In the general OFDM system, the two adjacent and repeated preamble symbols are used for the initial carrier-frequency synchronization while the performance of the frequency-offset estimation is bounded by quantization effect generated from analog-to-digital conversion at the receiver. This paper proposes a method in which one-symbol interval between two adjacent preamble symbols for the initial frequency synchronization is extended to multiple-symbol interval between non-adjacent symbols in an extent that phase ambiguity does not occur. In this paper, we also present '6' as optimal multiple symbol interval for the MB-OFDM system with 30 preamble symbols on 3-band hopping and with 4-bit A/D conversion at the receiver. Under the channel environments for the MB-OFDM UWB system, the simulation results show that the proposed estimation algorithm can achieve the initial estimation in offset precision less than 5 ppm.

A Study on Characteristics of A Diode Radiation Sensor for Portal Image of Therapy Radiation (치료방사선 Portal Image를 위한 다이오드 방사선 센서의 특성에 관한 연구)

  • Lee, Dong-Hun;Kwon, Jang-Woo;Hong, Seung-Hong
    • Journal of Sensor Science and Technology
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    • v.5 no.5
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    • pp.11-20
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    • 1996
  • In this paper, the characteristics of therapy radiation diode sensors have been studied by using therapy radiation from the MM22 microtron accelerator. The linearity, reproducibility and error ratio were measured for feasibility as a radiation detector. Energy dependence, sensitivity change after a amount of irradiation and output value according to a number of diodes were also measured for same purpose. We have formed pulse shaping of diode signal with nuclear instruments for portal image reconstruction. The percent depth dose ratio according to field size and depth was compared with that of the detector of a ion chamber. Using thirteen silicon diodes, we can directly read diode outputs on a computer monitor after A/D conversion with 16 channels analog to digital conversion board with 12 bit resolution. The possibility for portal image with diodes has been suggested from output comparison between output value with a human phantom and that without a human phantom.

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Spiral Drawing-based Real-time Crystallization Mosaic Tchnique (나선 드로잉 기반 실시간 결정화 모자이크 기법)

  • Kim, Jae Kyoung;Kim, Young Ho;Park, Jin Wan
    • Journal of the Korean Society for Computer Game
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    • v.31 no.4
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    • pp.137-144
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    • 2018
  • In the past, mosaics were made by laying cloth on the floor and manually tiling the tiles. However, due to recent developments in technology, the data storage method has evolved from analog to digital, so that image representation and conversion can be realized through computer. Also, various expression techniques of mosaic are developed, and it is also used as a method of art representation in digital. There are various studies on the production process of mosaic. The proposed method is a crystallization mosaic that spreads spirally in real time and uses 3D quartz as a tile element. Although existing researches are mostly focused on the purpose of rendering images in more detail, this technique combines untried spiral drawing and crystallization, and attempts to explore new expression techniques in 3D space by attempting a new mosaic method in 3D space. 'Spiral Crystallization Photo', based on this technique, was selected as Top27 in MWU Award 18 and exhibited at Unite Seoul 2018.

A Study On Hardware Design for High Speed High Precision Neutron Measurement (고속 고정밀 중성자 측정을 위한 하드웨어 설계에 관한 연구)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.1
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    • pp.61-67
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    • 2016
  • In this paper, a hardware design method is proposed for high speed high precision neutron radiation measurements. Our system is fabricated to use a high performance A/D Converter for digital data conversion of high precision and high speed analog signals. Using a neutron sensor, incident neutron radiation particles are detected; a precision microcurrent measurement module is also included: this module allows for more precise and rapid neutron radiation measurement design. The high speed high precision neutron measurement hardware system is composed of the neutron sensor, variable high voltage generator, microcurrent precision measurement component, embedded system, and display screen. The neutron sensor detects neutron radiation using high density polyethylene. The variable high voltage generator functions as a 0 ~ 2KV variable high voltage generator that is robust against heat and noise; this generator allows the neutron sensor to perform normally. The microcurrent precision measurement component employs a high performance A/D Converter to precisely and swiftly measure the high precision high speed microcurrent signal from the neutron sensor and to convert this analog signal into a digital one. The embedded system component performs multiple functions including neutron radiation measurement for high speed high precision neutron measurements, variable high voltage generator control, wired and wireless communications control, and data recording. Experiments using the proposed high speed high precision neutron measurement hardware shows that the hardware exhibits superior performance compared to that of conventional equipment with regard to measurement uncertainty, neutron measurement rate, accuracy, and neutron measurement range.

A 0.4-2GHz, Seamless Frequency Tracking controlled Dual-loop digital PLL (0.4-2GHz, Seamless 주파수 트래킹 제어 이중 루프 디지털 PLL)

  • Son, Young-Sang;Lim, Ji-Hoon;Ha, Jong-Chan;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.65-72
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    • 2008
  • This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

A 15b 50MS/s CMOS Pipeline A/D Converter Based on Digital Code-Error Calibration (디지털 코드 오차 보정 기법을 사용한 15비트 50MS/s CMOS 파이프라인 A/D 변환기)

  • Yoo, Pil-Seon;Lee, Kyung-Hoon;Yoon, Kun-Yong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.1-11
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    • 2008
  • This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.