• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.86-94
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• 2009

An idea to improve the performance of error correction with the amplification of input symbol errors is proposed to ease the mismatching problem which occurs in the hardware implementation of the differential analog PRML decoder. The differential analog PRML decoder is the decoder with two blocks of trellis diagram one of which is without branches of "0" and the other one is without the branches of "1". Decoding is performed by comparing the outputs of two blocks. The decoding error is likely to occur when the difference of two outputs is very small and the hardware implementation is not precise due to mismatching. The proposed idea is to increase the discrimination margin for the output "0" and "1" by amplifying the symbol error while the larger path metrics are saturated. To show the performance improvement of decoding with the proposed idea, simulation results are included

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.17-26
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• 2006

The analog Viterbi decoder for the PR (1 2 2 1) which is used for BVD read channel is designed with circular analog parallel circuits. Since the inter symbol interference is serious problem in the high density magnetic storage device or DVD, the PRML technology is normally employed for the purpose of minimizing the decoding error. The feature of the PRML technology is with the multi-level coding according to the predetermined combining rule among the neighboring symbols and with the decoding according to the known combining rule. Though the conventional PRML technology is implemented with the digital circuits, the recent trend towards this end is with the utilization of the analog circuits due to the requirements of higher speed and lower power in the DVD read channel. In this study, the Viterbi decoder which is the bottleneck of the PRML implementation is designed with the analog parallel circuit structure. The designed Viterbi decoder for the PR (1 2 2 1) signal shows 3 times faster in the speed and 1/3 times less in the power consumption than thoseoftheconventionaldigitalcounterpart.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.89-91
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• 2007

Multimedia service based on interactivity, personalization, multiple channels and community distinguishes IPTV from incumbent TV. But data encoding/decoding time and image frame processing should be considered in digital TV versus analog device. Especially channel zapping time is one of the most important parameters for the service quality of IPTV. This paper proposes the mechanism for decreasing the channel zapping time with multiple decoder and image frame processing. We also implemented the multi-group video community service system using IP multicasting function supporting interactive learning service.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.1
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• pp.31-40
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• 2021

The multi-channel video streaming system is an essential device for future ground combat vehicles. For the system, the application of digital interfaces is required instead of the direct analog method to support selectable multiple channels. However, due to the characteristics of the digital interfaces that require en/decoding and signal conversion, the system should support the ability to adapt to quality and delay requirements depending on how video data is utilized. To support addressed issue, this study designs and emulates the multi-channel compressed-video streaming system of ground combat vehicle's fire control system based on commercial standards. Using the system, this study analyzes the quality of video according to the rotational speed of the acquisition device and Glass-to-Glass (G2G) delay between video acquisition and display devices according to video compression rates. Through these experiments and analysis, this paper presents the design direction of the system having scalability on the latest technology while providing high-quality video data streaming flexibly.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• Journal of Broadcast Engineering
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• v.25 no.5
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• pp.758-769
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• 2020

Hybrid broadcasts utilizing heterogeneous networks can provide not only uniform broadcasting services but also various services using broadcast networks and communication networks. In particular, as content is consumed in various countries and regions, demands for personalized services continue to increase, and research on content insertion technology utilizing heterogeneous networks has been actively conducted. The most important technical challenge when inserting content based on heterogeneous networks is that the start of the inserted content, which replaces the original broadcast content at the time of content insertion, should proceed smoothly, and it must be able to accurately return to the original broadcast content. Currently, UHD broadcasting is converted to digital. However, since there is a system that supports the frame rate used in the analog method, when content insertion occurs in a conventional UHD broadcasting service, there is a problem in decoding the broadcast and inserted content. Since the replacement cost of the broadcasting system is astronomical, this paper proposes a content insertion method using by frame control that can support analog methods without replacing transmission equipment.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.217-227
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• 2003

This paper describes an implementation of the slide-show functionality, which is one of the services that can be provided by the Digital Multimedia Broadcasting (DMB). While the existing analog radio broadcasting services provide audio only, DMB slide-show is the functionality that can deliver still images associated with the audio. For example, it can deliver the photographs of the singer, album cover images, or the lyrics of the song that correspond to the audio. There are two modes for the transmission of the slide-show. Firstly. the program-associated data (PAD) field within the DMB audio frame can be utilized and secondly, the slide-show data can be transmitted, after being multiplexed, with other service data as individual data stream separated from the audio. This paper describes PC-based implementations of a transmitter-side module that inserts slide-show data into the PAD area within audio bitstream and a receiver-side application module that plays the slide-show through decoding the PAD within the received audio bitstream and demonstrates their validity through experiments.