• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.183-188
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• 2014

In this paper, the propagation effect of power supply uncertainty on the output of class-F power amplifier has been estimated. Also, a 1.9 GHz, 10 watt class-F power amplifier was measured to verify the estimation and to find the optimal biasing point. By approximating the propagation theory of uncertainties, the propagation effect of bias uncertainty was mathmatically calculated. As a result, the DC biases have propagated uncertainties of 15~70 mW. However, at the optimized bias point, the uncertainty in the output power could be dropped less than 15 mW while the output power has dropped by 0.37 dB.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.114-122
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• 1997

This paper describes the design and development of a smart digital load cell used forweighing installations. Sice the load cell sensor to be used is very sensitive for weight cariation, the load cell must have the temperature stability, low-drift and the high-resolution of the A/D conversion for accuracy. A new analog circuit which is controlled by one chip micro-processer has been developed to reduce the offset voltage and the drift characteristics of operational amplifiers, and has been adapted into the digital load cell. Also, a software algorithm has been developed to obtain the stable and accurate A/D conversion. This software includes a RS-485 communication program to control the digital load cell, which gives a capability of backing-up the calibration data and transferring control data. The simulation and evaluation of the designed digital load cell has been shown as having the good performance. which will give useful application to the weighing installations as a remote weighing sensor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Bulletin of the Korean Chemical Society
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• v.25 no.10
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• pp.1503-1507
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• 2004

New synthetic methodology of the saturated and unsaturated Er(III)-chelated prototype complexes based on benzoate and pentafluorobenzoate ligands was developed through ligand-exchange reaction. The saturated 8-coordinated Er(III) complexes exhibit stronger near-IR emission than those of the unsaturated 6-coordinated Er(III) complexes, obtained from the direct photoexcitation of Er ions with 488 nm. Three $H_2O$ molecules coordinated in the unsaturated 6-coordinated complexes seriously quenched the near IR emission by the harmonic vibration relaxation decay of O-H bonds. Also, the stronger emission of the Er(III) complexes was obtained by the indirect photoexcitation of ligands than by the direct photoexcitation of the Er(III) ions, due to the energy transfer between the excited ligand and the erbium ion. Furthermore, the saturated Er(III)-chelated complex with C-F bonds shows much stronger near IR emission than that of the saturated Er(III)-chelated complex with C-H bonds. It is attributed to the influence of C-F bonds on near IR emission.

• Journal of Digital Convergence
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• v.13 no.9
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• pp.219-224
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• 2015

The broadcasting communications service will accelerate its development with the convergence of broadcasting media and internet service. In the field of CATV network related technology, only those service providers will be able to survive in future, and they can combine available services in the most effective and economical way. This research aims to explain the CATV status of Korea and China and its technology trends. It also analyzes CMC(Cable Modem Concentrator) technology, suggested as one of the high-speed internet technology. CMC technology has the advantages of enhancing the transmission speed while using the existing basic structure of HFC network and expanding service area by adding amplifiers within CMC. The distance between coaxial cables is getting shorter with more concentrated areas in large cities in Korea. However, in China, the demand for long distance transmission service is increasing. CMC technology satisfies both short and long distance service subscribers without any geographical limitations. With these advantages, CMC technology is expected to generate lots of economic benefits if applied for the CATV network in the area of China, Middle East, and Southeast Asia.

• ETRI Journal
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• v.38 no.5
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• pp.981-987
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• 2016

We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.83-92
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• 2004

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.7
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• pp.18-23
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• 2000

An active phased away antenna consists of many channels including radiator and active circuitary that contains low noise amplifiers and phase shifters. Each channel has different initial phase shift and gain because of inequality in active circuitary itself, interface between radiator and active circuitary, beam forming network and other antenna configurations. This is an inherent problem in active phased away antenna, therefore each channels' initial phase shifts and gains should be calibrated for obtaining the designed radiation pattern and antenna gain. In this paper, an efficient calibration method for the active phased array antenna is presented. By performing the above method, thhe antenna gain is increased more than 2.0 dB after calibrating considerably unequal 12 channels' initial phase shifts and gains.