• The Journal of the Korea Contents Association
• /
• v.7 no.12
• /
• pp.262-272
• /
• 2007

SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.10
• /
• pp.1845-1852
• /
• 2008

The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.5
• /
• pp.58-65
• /
• 2007

As multimedia portable devices become popular, the amount of computation for processing data including video compression has significantly increased. Various researches for low power consumption of the mobile devices and real time processing have been reported. Motion Estimation is responsible for 67% of H.264 encoder complexity. In this research, a new circuit is designed for motion estimation. The new circuit uses motion prediction based on approximate SAD, Alternative Row Scan (ARS), DAU, and FDVS algorithms. Our new method can reduce the amount of computation by 75% when compared to multi-frame motion estimation suggested in JM8.2. Furthermore, optimal number and size of reference frame blocks are determined to reduce computation without affecting the PSNR. The proposed Motion Estimation method has been verified by using the hardware and software Co-Simulation with iPROVE. It can process 30 CIF frames/sec at 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.11
• /
• pp.29-36
• /
• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of KIISE:Software and Applications
• /
• v.33 no.4
• /
• pp.411-417
• /
• 2006

Motion Estimation (ME) is an important part of video coding process and it takes the largest amount of computation in video compression. Half-pixel and quarter-pixel motion estimation can improve the video compression rate at the cost of higher computational complexity In this paper, we suggest a new efficient low-complexity algorithm for half-pixel and quarter pixel motion estimation. It is based on the experimental results that the sum of absolute differences(SAD) shows parabolic shape and thus can be approximated by using interpolation techniques. The sub-pixel motion vector is searched from the minimum SAD integer-pixel motion vector. The sub-pixel search direction is determined toward the neighboring pixel with the lowest SAD among 8 neighbors. Experimental results show that more than 20% reduction in computation time can be achieved without affecting the quality of video.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.3
• /
• pp.93-102
• /
• 2008

In this paper, we propose a rate control algorithm for constant quality real time video coding. To achieve constant quality, previous algorithm exploit mean absolute of difference(MAD) as measure of frame complexity. However, if scene is abruptly changed or if quantization parameter is not constant, encoder produces various output bits with same MAD. Therefore we know that MAD does not appropriately reflect characteristic of frame. To solve this problem, we exploit model parameter as measure of frame complexity. Because model parameter means slope between output bits and MAD, it reflects correctly complexity of frame. And because previous model, R-MAD model, is not considered quantization parameter, as quantization parameter increases or decreases, model parameter of frame also vary. So model parameter obtained using previous model cannot reflect internal characteristic of video. We solve this problem using proposed model, which is considered quantization parameter. Experiment results show that our algorithm provide better performance, in terms of quality smoothness than previous algorithm. Especially, when scene is abruptly changed, our algorithm alleviates quality drop.

• Journal of Broadcast Engineering
• /
• v.27 no.3
• /
• pp.361-368
• /
• 2022

Quaternary tree plus multi-type tree (QT+MTT) structure was adopted in the Versatile Video Coding (VVC) standard as a block partitioning tool. QT+MTT provides excellent coding gain; however, it has huge encoding complexity due to the flexibility of the binary tree (BT) and ternary tree (TT) splits. This paper proposes a fast inter coding unit (CU) partitioning algorithm for BT and TT split types based on prediction accuracy functions using the mean of the absolute error (MAE). The MAE-based decision model was established to achieve a consistent time-saving encoding with stable coding loss for a practical low complexity VVC encoder. Experimental results under random access test configuration showed that the proposed algorithm achieved the encoding time saving from 24.0% to 31.7% with increasing luminance Bjontegaard delta (BD) rate from 1.0% to 2.1%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2008.11a
• /
• pp.267-270
• /
• 2008

H.264|AVC는 인트라 부호화 효율을 높이기 위해 공간 영역에서 주변 화소를 이용하여 다양한 방향에 대한 율-왜곡 최적화 기법을 사용하여 최적의 인트라 예측 모드를 선택한다. 하지만 율-왜곡 최적화 기법을 사용함에 따라 인트라 부호화에 높은 복잡도가 필요하게 되었다. 따라서 본 논문에서는 인트라 예측 모드 결정의 연산 복잡도를 감소시키고자 사전에 인트라 4x4 예측 모드들의 SATD(Sum of Absolute Transform Difference)를 계산하여 조기에 최우선 모드(Most Probable Mode)를 선택하는 방법을 제안하고, SATD의 값에 따라 제한된 후보 모드에 대해서만 율-왜곡 최적화를 수행하여 연산 복잡도를 감소하는 방법을 제안한다. 또한 Vertical, Horizontal 그리고 DC모드는 인트라 $4{\times}4$와 인트라 $16{\times}16$의 공통적인 모드이므로 인트라 $4{\times}4$에서 계산되어진 SATD값을 이용하여 인트라 $16{\times}16$에서의 SAD 계산 복잡도를 줄이는 방법을 제안한다. 본 논문에서 제안하는 빠른 인트라 예측 모드 결정 기법은 연산 복잡도는 평균 61.4% 감소 시킨 반면 부호화 손실은 평균 3.09%에 불과하였다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.8 no.4
• /
• pp.336-343
• /
• 2003

Generally, brushless DC motor(BLDCM) driving system uses hall sensors or encoders as the mechanical position or speed sensors. It is necessary to achieve the information's of rotor position for driving trapezoidal type brushless DC motor without any position sensor. This paper proposes a sensorless driving system with absolute rotor position detecting circuit which acquires both commutating phase and commutating time by analyzing motor phase voltages. Proposed system is applied to a 10k[W] rating motor which actually used in Hybrid Electric Vehicles. The experimental results will show the validity of the proposed system and the practical use of proposed sensorless drive.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.10 no.2
• /
• pp.148-154
• /
• 2005

As the exciting point of each phase is determined by the position of rotor, the rotor's accurate position-information is needed for the Switched Reluctance Motor(SRM). When using an absolute-encoder or a resolver, to detect the location of rotor the initial starting is possible, as early sensing of rotor's location is possible. However, this is not appropriate, considering the economical efficiency, and in case of using the incremental-encoder, there's a problem at initial starting as it is not easy to track down the location of rotor at the very beginning. When using Hall-ICs, there's a fault, as it needs a special ring magnet. Considering the initial starting and economical efficiency, the optical sensor technique using a slotted-disk and an opto-interrupter is appropriate, however, this method needs three opto-interrupters and a slotted-disk when using the 6/4 pole SRM. Nevertheless, in this paper, it used only two optical sensors to operate 6/4 pole SRM and made the start up and also forward and reverse operation possible. By excluding the slotted-disc md shortening a optical sensor, it improved the convenience and economical efficiency of the production. Also, as the space for slotted-disc is no more needed, it was able to reduce the size of motor.