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An Efficient Architecture of Transform & Quantization Module in MPEG-4 Video Code  

서기범 (우송대학교 전자정보통신공학과)
윤동원 (대전대학교 전자정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.11, 2003 , pp. 29-36 More about this Journal
Abstract
In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.
Keywords
DCT; AC/DC Prediction; LOW Power;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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