• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.197-206
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• 1997

A SiC epilayer on the 6H-SiC crystal substrate was grown by chemical vapor deposition (CVD). The crystal structure of the SiC epilayer was investigated by using the X-ray diffraction patterns and the Roman scattering spectroscopy. The SiC epilayer on the 6H-SiC substrate was grown to be homoepilayer by CVD. In order to distinguish a certain SiC polytype mixed in the SiC crystal grown by the modified Lely method, we have calculated the X-ray diffraction intensities and Brags angles of the typical SiC crystal powders. By comparing the measured X-ray diffraction pattern with the calculated ones, it was identified that the SiC crystal grown by the modified Lely method was the 6H-SiC crystal mixed some 15R-SiC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Journal of the Korean Vacuum Society
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• v.4 no.4
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• pp.350-357
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• 1995

SiH4와 Si2H6를 1-3 Torr 정도의 저압에서 열분해시켰을 때, 반응물의 농도 변화를 살펴보고 이로부터 열분해의 반응 기구를 예측하였다. 분석기로는 질량 분석기를 이용하였으며, 분해 온도 범위는 SiH4의 경우는 $350~475^{\circ}C$, Si2H6의 경우는 275-375$^{\circ}C$이었다. SiH4의 분해 양상은 1차 비가역 반응에 잘 들어 맞았으며, 그 속도 상수는 문헌에 보고되어 있는 상압에서의 속도보다 작았다. Si2H6는 낮은 온도 범위에서도 잘 분해되었으며, 중간 생성물로 많은 양의 SiH4를 만들었다. 그리고, SiH4는 고분자화되는 반응을 거치지 않고 고체실리콘을 생성하지만, Si2H6는 중간 생성물로 만들어진 SiH4와 SiH2에 의하여, 고분자화 반응을 거쳐서 고체실리콘을 만들 수 있음을 알았다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.128.1-128.1
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• 2011

In amorphous silicon and crystalline silicon(a-Si:H/c-Si) heterojuction solar cells, intrinsic hydrogenated amorphous silicon(a-Si:H) films play an important role to passivate the crystalline silicon wafer surfaces. We have studied the correlation between the surface passivation quality and nature of the Si-H bonding at the a-Si:H/c-Si interface. The samples were obtained by VHF-CVD under different deposition conditions. The passivation quality and analysis of all structures studied was performed by means of quasi steady state photoconductance(QSSPC) methods and fourier transform infrared spectrometer(FTIR) measurements respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• Journal of the Korean institute of surface engineering
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• v.53 no.5
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• pp.201-206
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• 2020

A SiOxCy(-H) thin film was synthesized by atmospheric pressure dielectric barrier discharge(APDBD), and a SiO₂-like layer was formed on the surface of the film by oxidation treatment using oxygen plasma. Hexamethylcyclotrisiloxane was used as a precursor for the SiOxCy(-H) synthesis, and He gas was used for stabilizing APDBD. Oxygen permeability was evaluated by forming an oxidized SiOxCy(-H) thin film on a PET film. When the single-layer oxidized SiOxCy(-H) film was coated on the PET, the oxygen gas permeability decreased by 46% compared with bare PET. In case of three-layer oxidized SiOxCy(-H) film, the oxygen gas permeability decreased by 73%. The oxygen permeability was affected by the thickness of the SiO₂-like layer formed by oxidation treatment rather than the thickness of the SiOxCy(-H) film. The excellent corrosion resistance was demonstrated by coating an oxidized SiOxCy(-H) thin film on the silver-coated aluminum PCB for light emitting diode (LED).

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.14-21
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• 1993

MODFETs using the heterostructure of phosphorous-contained a-SiN:H: and undoped a-Si:H films have been fabricated by PECVD of SiH$_{4}$, PH$_{3}$ gases. Thecharacteristics of the devices have been invetigated and compared with conventional TFTs(CTFTs). The threshold voltage of the MODFETs was smaller than that of CTFTs, in the case of the devices using the a-SiN:H film with the relatively high phosphorous content, the threshold voltage was negative and the operation of the devices followed the depletion mode. On the other hand, on/off current ratio of the MODFETs was more than one order of magnitude higher than the CTFTs, and the field effect mobility of the former was approximately two times as high as that of the latter.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.117-124
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• 1996

The .mu.c-Si:H films have been deposited by PeCVD at the various conditions such as hydrogen dilution ratio, substrate temperature and RF power density. Then, we studied their electrical and optical properties. Top gate hydrogenated micro-crystalline silicon thin film transistors($\mu$c-Si:H TFTs) using $\mu$-Si:H and a-SiN:H films have been fabricated by FECVD. The electrical characteristics of the devices have been investigated by semiconductor parameter analyzer and compared with amorphous silicon thin film transistors (a-Si:H TFTs). In this study, on/off current ratio, threshold voltage and the field effect mobility of the $\mu$c-Si:H TFT were $3{\times}10^{4}$, 5.06V and 0.94cm$^{2}$Vs, respectively.

• Solar Energy
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• v.20 no.1
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• pp.11-20
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• 2000

To get more insight into the buffering effects of the p-${\mu}c$-Si:H Inserted at the p-a-SiC:H/i-a-Si:H interface, we present a systematic numerical simulation using Gummel-Schafetter method. The reduced recombination loss at the p/i interface due to a constant bandgap buffer is analysed in terms of the variation of the p/i Interface region with a short lifetime and the characterisitics of the buffer such as mobility bandgap, acceptor concentration, and D-state density. The numerical modeling on the constant bandgap buffer demonstrates clearly that the buffering effects of the thin p-${\mu}c$-Si:H originate from the shrinkage of highly defective region with a short lifetime in the vicinity of the p/i interface.