• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.1
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• pp.57-62
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• 2002

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

• ETRI Journal
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• v.33 no.6
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.6 s.261
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• pp.522-530
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was proposed, which are composed of data collection, data analysis, improvement action, verification, and implement control. The partition check method and the composition analysis for data collection and data analysis were respectively used in the main board and the cellular phone module production lines. And these methods were evaluated by the variation of yield loss between before and after improvement action. In case that the partition check method was applied, the critical process step was selected and yield loss reduction through improvement actions was observed. While in case that the composition analysis was applied, the critical sources were selected and yield loss reduction through improvement actions was also investigated. From these results, it is concluded that the partition check and the composition analysis are effective solutions for particle contamination control in the cleanroom production lines.

• ETRI Journal
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• v.34 no.3
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• Journal of Industrial Technology
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• v.39 no.1
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• pp.7-14
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• 2019

Carbon nanotubes (CNT) on metal substrates are definitely beneficial because they can maintain robust mechanical stability and high conductivity between CNT and metal interfaces. Here, we report direct growth of CNT on Ni-based superalloy, Inconel 600, using thermal chemical vapor deposition (CVD) with acetylene feedstock in the growth temperature range of $400-725^{\circ}C$. Furthermore, we studied the effect of substrate pretreatment on the growth yield enhancement and growth temperature decrease of CNT on Inconel 600. Activation energy (AE) for CNT growth was estimated from the CNT height change with respect to the growth temperature. The AE values significantly decreased from 205.03 to 24.35 kJ/mol by the pretreatment of thermal oxidation of Inconel substrate at $725^{\circ}C$ under ambient. Higher oxidation temperature tends to have lower activation energy. The results have shown the importance of pretreatment temperature on CNT growth yield and growth temperature decrease.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2333-2337
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was considered, which is composed of data collection, data analysis, improvement action, verification, and implement control. The composition analysis for data collection and data analysis was used in the cellular phone module packaging lines. And this method was evaluated by the variation of yield loss between before and after improvement action. In case that the composition analysis was applied, the critical sources were selected and yield loss reduction through improvement actions was also investigated. From these results, it is concluded that the composition analysis is effective solutions for particle contamination control in the cleanroom.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2338-2343
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was proposed, which are composed of data collection, data analysis, improvement action, verification, and implement control. The partition check method for data collection and data analysis was used in the cellular phone module production lines. And this method was evaluated by the variation of yield loss between before and after improvement action. In case that the partition check method was applied, the critical process step was selected and yield loss reduction through improvement actions was observed. From these results, it is concluded that the partition check method is effective solution for particle contamination control in the cleanroom production lines.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.