• 한국시뮬레이션학회논문지
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• 제14권1호
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• 대한산업공학회지
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• 제28권1호
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• pp.57-62
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• 2002

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

• ETRI Journal
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• 제33권6호
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• 대한기계학회논문집B
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• 제31권6호
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• pp.522-530
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was proposed, which are composed of data collection, data analysis, improvement action, verification, and implement control. The partition check method and the composition analysis for data collection and data analysis were respectively used in the main board and the cellular phone module production lines. And these methods were evaluated by the variation of yield loss between before and after improvement action. In case that the partition check method was applied, the critical process step was selected and yield loss reduction through improvement actions was observed. While in case that the composition analysis was applied, the critical sources were selected and yield loss reduction through improvement actions was also investigated. From these results, it is concluded that the partition check and the composition analysis are effective solutions for particle contamination control in the cleanroom production lines.

• ETRI Journal
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• 제34권3호
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• 산업기술연구
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• 제39권1호
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• pp.7-14
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• 2019

Carbon nanotubes (CNT) on metal substrates are definitely beneficial because they can maintain robust mechanical stability and high conductivity between CNT and metal interfaces. Here, we report direct growth of CNT on Ni-based superalloy, Inconel 600, using thermal chemical vapor deposition (CVD) with acetylene feedstock in the growth temperature range of $400-725^{\circ}C$. Furthermore, we studied the effect of substrate pretreatment on the growth yield enhancement and growth temperature decrease of CNT on Inconel 600. Activation energy (AE) for CNT growth was estimated from the CNT height change with respect to the growth temperature. The AE values significantly decreased from 205.03 to 24.35 kJ/mol by the pretreatment of thermal oxidation of Inconel substrate at $725^{\circ}C$ under ambient. Higher oxidation temperature tends to have lower activation energy. The results have shown the importance of pretreatment temperature on CNT growth yield and growth temperature decrease.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2333-2337
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was considered, which is composed of data collection, data analysis, improvement action, verification, and implement control. The composition analysis for data collection and data analysis was used in the cellular phone module packaging lines. And this method was evaluated by the variation of yield loss between before and after improvement action. In case that the composition analysis was applied, the critical sources were selected and yield loss reduction through improvement actions was also investigated. From these results, it is concluded that the composition analysis is effective solutions for particle contamination control in the cleanroom.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2338-2343
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• 2007

The practical studies on the method of particle contamination control for yield enhancement in the cleanroom were carried out. The method of the contamination control was proposed, which are composed of data collection, data analysis, improvement action, verification, and implement control. The partition check method for data collection and data analysis was used in the cellular phone module production lines. And this method was evaluated by the variation of yield loss between before and after improvement action. In case that the partition check method was applied, the critical process step was selected and yield loss reduction through improvement actions was observed. From these results, it is concluded that the partition check method is effective solution for particle contamination control in the cleanroom production lines.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.30-36
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• 2011

많은 반도체 회사들이 메모리 층 사이에서 수직 버스의 역할을 하는 TSV를 사용한 3차원 메모리를 개발하고 있다. 3차원 메모리는 KGD로 이루어지며, 만약 추가 고장이 접합 공정 중에 발생한다면, 반드시 수리되어야 한다. 공유 예비 셀을 가지는 3차원 메모리의 수율을 증진시키기 위해서, 3차원 메모리 내의 메모리 다이를 효과적으로 적층하는 다이 매칭 방법이 필요하다. 본 논문에서는 공유 예비 셀을 가지는 3차원 메모리의 수율 증진을 위해 접합 공정에서 추가 고장이 발생하는 경우를 고려한 다이 매칭 방법을 제안한다. 세 가지 경계 제한 조건이 제안하는 다이 매칭 방법에서 사용된다. 이 조건은 3차원 메모리를 제작하기 위해 선택하는 메모리 다이의 검색 범위를 제한한다. 시뮬레이션 결과는 제안하는 다이 매칭 방법이 3차원 메모리의 수율을 크게 향상 시킬 수 있음을 보여 준다.