• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.472-475
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• 2002

A Rogowski coil can measure alternating currents from a few amps to over 1 million amps in a frequency range from less than 0.1 Hz to about lMhz. A Rogowski coil provides an induced output voltage which is proportional to the rate of change of the primary current enclosed by the flexible or the rigid coil-loop. Therefore, it is necessary to integrate the output voltage in order to produce a voltage proportional to the current. Also. it can reproduce the current waveform on an oscilloscope or any type of data acquisition device. This paper describes the practical design of the combination of a Rogowski coil and an integrator which provides a versatile current measuring system to accommodate a wide range of frequencies, current levels and conductor sizes.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.119-122
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• 2005

A algorithm for control and performance of a pulse-density-modulated (PDM) series-resonant voltage source inverter developed for corona-dischange precesses is presented. The PDM inverter produces either a square-wave ac-voltage state or a zero-voltage state at its ac terminals to control the average output voltage under constant dc voltage and operating frequency. Moreover it can achieve zero-current-switching (ZCS) and zero-voltage-switching (ZVS) in all the operating condition for a reduction of switching lost. Even though the corona discharge load with a strong nonlinear characteristics, new high frequency resonant inverter is shown the wide range power control from 5% to 100%.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.193-194
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• 2012

The bidirectional boost-buck chopper type AC voltage regulator is presented in this paper. The main characteristic of the AC chopper is the fact that it generates an output AC voltage larger or lower than the input AC one, depending of the instantaneous duty-cycle. Boost-buck chopper type AC voltage regulator, derived from the DC chopper modulated method, is a kind of direct AC-AC voltage converter and has many advantages: such as fast response speed, low harmonics and high power factor. It adopts high switching frequency AC chopper technique and can do wide range step less AC voltage regulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.11
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• pp.676-680
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• 2016

This paper describes a low voltage detection circuit used in the semiconductor chips. The circuit was composed of a detection part of the CMOS structure as three stages and two inverters. The output of the low voltage detection circuit become to 'high' from 'low', when the power supply voltage falls below 80%. When the power supply voltage is 5 V, it was detected at 4 V point. The proposed low voltage detection circuit can be easily applied only by changing the resister and the capacitor without structural change in a wide range of power supply voltage.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of Power Electronics
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• v.8 no.4
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• pp.309-316
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• 2008

In this paper, new topology is proposed that can dramatically reduce the converter power rating and increase the efficiency of total PV system. Since the output voltage of PV module has very wide voltage range, in general, the DC/DC converter is used to get constant high DC voltage. According to analysis of PV characteristics, in proposed topology, only 20% power of total PV system power is needed for DC/DC converter. DC/DC converter used in proposed topology has flat efficiency curve at all load range and very high efficiency characteristics. The total system efficiency is the product of that of converter and that of inverter. In proposed topology, because the converter efficiency curve is flat all load range, the total system efficiency at the low power range is dramatically improved. The proposed topology is implemented for 200kW PCS system. This system has only three DC/DC converters with 20kW power rating each other. It is only one-third of total system power. The experiment results show that the proposed topology has good performance.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.836-842
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• 2005

This paper presents a power supply of railway signal system using a Z-source inverter. The Z-source inverter overcomes the conceptual and theoretical barriers and limitations of the tradition voltage-source inverter and current-source inverter and provides novel power conversion concept. The Z-source inverter is a Buck-Boost inverter that has a wide range of obtainable voltage.