• 전기학회논문지
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• 제61권2호
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.965_966
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• 2009

In this paper, a new soft-switching Two-switch Forward converter topology has been proposed. Compared with conventional two-switch forward converter, the proposed converter employs an auxiliary switch and a clamp capacitor to instead of two reset diodes, not only its duty cycle can exceed 0.5 to achieve wide range input voltage, but also soft switching can be achieved for all switches. Especially, voltage stress across main switches can be clamped at $1/2V_{in}$, voltage stress across auxiliary switch can be clamped at $V_{in}$. In addition, due to clamp capacitor series with the transformer, duty ratio can be extended with equation $V_o=\frac{V_{in}(1-D}D{N}$. Therefore, as a kind of better cost-effective approach, it is very attractive for high input, wide range and high efficiency application.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• 전력전자학회논문지
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• 제20권4호
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• pp.313-320
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• 2015

This study deals with a bidirectional interleaved soft switching DC-DC converter for a wide range of input voltages. The proposed converter operates in complementary switching with the purpose of inductor size reduction and zero-voltage switching (ZVS) operation. The current ripple related to complementary switching is minimized by three-phase interleaved operation. The main characteristics of the proposed topology are its soft-switching method of operation and its simple structure. The soft-switching operation and the system efficiency of the proposed converter are verified by experimental results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.21-24
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• 2002

This paper presents a fully integrated, wide tuning range differential CMOS voltage-controlled oscillator, tuned by pMOS-varactors. VCO utilizing a novel tuning scheme is reported. Both coarse digital tuning and fine analog tuning are achieved using pMOS-varactors. The VCO were implemented in a 0.18-fm standard CMOS process. The VCO tuned from 1.8㎓ to 2.55㎓ through 2-bit digital and analog input. At 1.8V power supply voltage and a total power dissipation of 8mW, the VCO features a phase noise of -126㏈c/㎐ at 3㎒ frequency offset.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.587-590
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• 2005

We investigated the input impedance characteristics of UHF-band RFID tag chip for increased reading range. A voltage multiplier designed using 0.4 ${\mu}m$ $zero-V_T$ MOSFET showed that DC output voltage of 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance level for maximum reading distance using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages of the voltage multiplier, and thus, the impedance level required for the tag antenna can be obtained in presence of other tag circuit blocks.

• Journal of Power Electronics
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• 제18권5호
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• pp.1303-1314
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• 2018

To match the dynamic lower voltage of a fuel cell stack and the required constant higher voltage (400V) of a DC bus, an H-type structural Boost three-level DC-DC converter with a wide voltage-gain range (HS-BTL) is presented in this paper. When compared with the traditional flying-capacitor Boost three-level DC-DC converter, the proposed converter can obtain a higher voltage-gain and does not require a complicate control for the flying-capacitor voltage balance. Moreover, the proposed converter, which can draw a continuous and low-rippled current from an input source, has the advantages of a wide voltage-gain range and low voltage stress for power semiconductors. The operating principle, parameters design and a comparison with other converters are presented and analyzed. Experimental results are also given to verify the aforementioned characteristics and theoretical analysis. The proposed converter is suitable for application of fuel cell systems.

• Journal of Power Electronics
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• 제18권2호
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• pp.640-650
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• 2018

A TRIAC dimmable LED driver with a wide tuning range and a two-stage uniform dimming scheme is proposed in this paper. To solve the restricted dimming range problem caused by the limited conduction ratio of TRIAC dimmers, a conduction ratio compensation technique is introduced, which can increase the output current up to the rated output current when the TRIAC dimmer turns to the maximum conduction ratio. For further optimization, a two-stage uniform dimming diagram with a rapid dimming curve and a slow dimming curve is designed to make the LED driver regulated visually uniform in the whole adjustable range of the TRIAC dimmer. The proposed control chip is fabricated in a TSMC $0.35{\mu}m$ 5V/650V CMOS/LDMOS process, and verified on a 21V/500mA circuit prototype. The test results show that, in the 90V/60Hz~132V/60Hz ac input range, the voltage linear regulation is 2.6%, the power factor is 99.5% and the efficiency is 83%. Moreover, in the dimming mode, the dimming rate is less than 1% when the maximum dimming current is 516mA and the minimum dimming current is only about 5mA.