• 한국세라믹학회지
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• 제46권5호
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• pp.510-514
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• 2009

The microstructure and mechanical behavior of deformed silicon were characterized using transmission electron microscopy and nanoindentation. Structural defects such as stacking faults and dislocations were observed through the diffraction contrast in transmission electron microscopy. The mechanical properties of deformed Si and 111 Si wafer and mechanical behaviors during contact loading were also characterized using nanoindentation. The hardness values of silicon samples were ${\sim}10$ GPa and the elastic modulus were varied with indentation conditions. Elbow or pop-out behaviors were found in load-displacement curves of silicon samples during nanoindentation. Deformed silicon showed 'pop-out' behavior more frequently under the load of 10 mN, which is attributed to the structural defects in deformed silicon.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.189.1-189.1
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• 2013

Titanium dioxide (TiO2) is a wide bandgap semiconductor possessing photochemical stability and thus widely used for photocatalysis. However, enhancing photocatalytic efficiency is still a challenging issue. In general, the efficiency is affected by physio-chemical properties such as crystalline phase, crystallinity, exposed crystal facets, crystallite size, porosity, and surface/bulk defects. Here we propose an alternative approach to enhance the efficiency by studying interfaces between thin TiO2 layers to be stacked; that is, the interfacial phenomena influencing on the formation of porous structures, controlling crystallite sizes and crystallinity. To do so, multi-layered TiO2 thin films were fabricated by using a sol-gel method. Specifically, a single TiO2 thin layer with a thickness range of 20~40 nm was deposited on a silicon wafer and annealed at $600^{\circ}C$. The processing step was repeated up to 6 times. The resulting structures were characterized by conventional electron microscopes, and followed by carrying out photocatalytic performances. The multi-layered TiO2 thin films with enhancing photocatalytic efficiency can be readily applied for bio- and gas sensing devices.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 대한금속재료학회지
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• 제48권7호
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• 대한금속재료학회지
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• 제50권2호
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Korean Chemical Engineering Research
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• 제47권1호
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• pp.1-10
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• 2009

작은 크기의 고기능성 휴대용 전자기기 수요의 급증에 따라 기존에 사용되던 수평구조의 2차원 칩의 크기를 줄이는 것은, 전기 배선의 신호지연 증가로 한계에 도달했다. 이러한 문제를 해결하기 위해 칩들을 수직으로 적층한 뒤, 수평 구조의 긴 신호배선을 짧은 수직 배선으로 만들어 신호지연을 최소화하는 3차원 칩 적층기술이 새롭게 제안되었다. 3차원 칩의 개발을 위해서는 기존에 사용되던 반도체 공정들뿐 아니라 실리콘 관통 전극 기술, 웨이퍼 박화 기술, 웨이퍼 정렬 및 본딩 기술 등의 새로운 공정들이 개발되어야 하며 위 기술들의 표준 공정을 개발하기 위한 노력이 현재 활발히 진행되고 있다. 현재까지 4~8개의 단일칩을 수직으로 적층한 DRAM/NAND 칩, 및 메모리 칩과 CPU 칩을 한꺼번에 적층한 구조의 성공적인 개발 결과가 보고되었다. 본 총설에서는 이러한 3차원 칩 적층의 기본 원리와 구조, 적층에 필요한 중요 기술들에 대한 소개, 개발 현황 및 앞으로 나아갈 방향에 대해 논의하고자 한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.121-121
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• 2000

반도체 산업의 발달에 따라 소자의 보다 빠른 동작 속도와 큰 집적도를 갖은 ULSI 구조를 얻기 위해, 새로운 금속배선 재료가 요구되고 있다. 기존의 금속 배선인 Al 및 Al 합금은 비교적 낮은 비저항과 박막형성의 용이함으로 인하여 현재까지 금속배선 재료로 사용되고 있으나, 고집적화에 따라 RC Time Delay와 Electromigration의 문제점을 들어내었다. 이러한 문제를 해결할 새로운 배선 재료로 Al보다 낮은 비저항을 가지며, electromigration 저항성을 갖는 Cu 금속배선 재료가 활발히 연구되고 있다. 본 실험에서는 (100) Si 웨이퍼를 기판으로 사용하였으며, 각층은 SiO2/Si3N4/EP Cu/Seed Cu/ TaN/SiO2/Si wafer 상태로 증착하였다. 확산방지막으로 TaN을 사용하였고, seed Cu는 sputtering 으로 증착하였으며, seed Cu 만으로 된 박막과 seed Cu + electro plating Cu로 구성된 박막을 제작하였다. 제작 완료된 박막은 N2 분위기에서 20$0^{\circ}C$ 120 min, 45$0^{\circ}C$ 60min 동안 열처리하여 Cu 박막의 조직 변화를 TEM 및 여러 분석방법을 이용하여 분석하였다. Plan-view TEM결과, 45$0^{\circ}C$, 60min 열처리함에 따라 결정립 성장이 일어난 것을 확인 할 수 있었다. 그러나, 성장후에도 twin boundary, stacking fault, dislocation, small defect 등은 여전히 남아 있음이 관찰된다. 그림 1(a)는 as-deposit 상태이며, 그림 1(b)는 45$0^{\circ}C$, 60min 열처리한 plan-view TEM 사진이다.

• Current Photovoltaic Research
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• 제6권4호
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• pp.109-118
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• 2018

Silicon (Si) solar cells are the most successful technology which are ruling the present photovoltaic (PV) market. In that essence, multijunction (MJ) solar cells provided a new path to improve the state-of-art efficiencies. There are so many hurdles to grow the MJ III-V materials on Si substrate as Si with other materials often demands similar qualities, so it is needed to realize the prospective of Si tandem solar cells. However, Si tandem solar cells with MJ III-V materials have shown the maximum efficiency of 30 %. This work reviews the development of the III-V/Si solar cells with the synopsis of various growth mechanisms i.e hetero-epitaxy, wafer bonding and mechanical stacking of III-V materials on Si substrate. Theoretical approaches to design efficient tandem cell with an analysis of state-of-art silicon solar cells, sensitivity, difficulties and their probable solutions are discussed in this work. An analytical model which yields the practical efficiency values to design the high efficiency III-V/Si solar cells is described briefly.

• 한국표면공학회지
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• 제56권3호
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.