• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.22 no.2
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• pp.173-183
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• 1998

An optimization procedure to find the inlet concentration profile that yields the most uniform deposition rate in a cylindrical CVD chamber has been developed. Assuming that the chemical reaction time is negligibly small, a SIMPLE based finite-volume method is adopted to solve the fully elliptic equations for momentum, temperature, and concentration. The inlet concentration profile is expressed by a linear combination of Chebyshev polynomials and the coefficients of which are determined by the local random search technique. It is shown that the present method is very effective in improving the uniformity of the deposition rate, especially when Re is high and/or the wafer is placed close to the inlet. The optimal profiles have been obtained for various Re, Gr, and geometry combinations.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• Tribology and Lubricants
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• v.38 no.4
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• pp.152-161
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• 2022

Chemical mechanical planarization (CMP) is a technology that planarizes the surfaces of semiconductor devices using chemical reaction and mechanical material removal, and it is an essential process in manufacturing highly integrated semiconductors. In the CMP process, a conditioning process using a diamond conditioner is applied to remove by-products generated during processing and ensure the surface roughness of the CMP pad. In previous studies, prediction of pad wear by CMP conditioning has depended on numerical analysis studies based on mathematical simulation. In this study, using an artificial neural network, the ratio of conditioner coverage to the distance between centers in the conditioning system is input, and the average conditioning density, standard deviation, nonuniformity (NU), and conditioning density distribution are trained as targets. The result of training seems to predict the target data well, although the average conditioning density, standard deviation, and NU in the contact area of wafer and pad and all areas of the pad have some errors. In addition, in the case of NU, the prediction calculated from the training results of the average conditioning density and standard deviation can reduce the error of training compared with the results predicted through training. The results of training on the conditioning density profile generally follow the target data well, confirming that the shape of the conditioning density profile can be predicted.

• Tribology and Lubricants
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• v.38 no.1
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• pp.1-7
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• 2022

Chemical-mechanical polishing (CMP) process is a semiconductor process that planarizes a wafer surface using mechanical friction between a polishing pad and a substrate surface during a specific chemical reaction. During the CMP process, polishing pad conditioning is applied to prevent the rapid degradation of the polishing quality caused by polishing pad glazing through repeated material removal processes. However, during the conditioning process, uneven wear on the polishing pad is inevitable because the disk on which diamond particles are electrodeposited is used. Therefore, the abrasion of the polishing pad should be considered not only for the variables during the conditioning process but also when designing the CMP conditioning system. In this study, three design variables of the conditioning system were analyzed, and the effect on the pad wear profile during conditioning was investigated. The three design variables considered in this study were the length of the conditioner arm, diameter of the conditioner disk, and distance between centers. The Taguchi method was used for the experimental design. The effect of the three design variables on pad wear and uniformity was assessed, and new variables used in conditioning system design were proposed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.338-338
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• 2013

Monolithic three-dimensional integrated circuits (3D-ICs) 구현 시 bonding 과정에서 발생되는 aluminum (Al) 이나 copper (Cu) 등의 interconnect metal의 확산, 열적 스트레스, 결함의 발생, 도펀트 재분포와 같은 문제들을 피하기 위해서는 저온 공정이 필수적이다. 지금까지는 polymer 기반의 bonding이나 Cu/Cu와 같은 metal 기반의 bonding 등과 같은 저온 bonding 방법이 연구되어 왔다. 그러나 이와 같은 bonding 공정들은 공정 시 void와 같은 문제가 발생하거나 공정을 위한 특수한 장비가 필수적이다. 반면, 두 물질의 합금을 이용해 녹는점을 낮추는 eutectic bonding 공정은 저온에서 공정이 가능할 뿐만 아니라 void의 발생 없이 강한 bonding 강도를 얻을 수 있다. Aluminum-germanium (Al-Ge) 및 aluminum-indium (Al-In) 등의 조합이 eutectic bonding에 이용되어 각각 $424^{\circ}C$ 및 $454^{\circ}C$의 저온 공정을 성취하였으나 여전히 $400^{\circ}C$이상의 eutectic 온도로 인해 3D-ICs의 구현 시에는 적용이 불가능하다. 이러한 metal 조합들에 비해 indium (In)과 tin (Sn)은 각각 $156^{\circ}C$ 및 $232^{\circ}C$로 굉장히 낮은 녹는점을 가지고 있기 때문에 In-Sn 조합은 약 $120^{\circ}C$ 정도의 상당히 낮은eutectic 온도를 갖는다. 따라서 본 연구팀은 In-Sn 조합을 이용하여 $200^{\circ}C$ 이하에서monolithic 3D-IC 구현 시 사용될 eutectic bonding 공정을 개발하였다. 100 nm SiO2가 증착된 Si wafer 위에 50 nm Ti 및 410 nm In을 증착하고, 다른Si wafer 위에 50 nm Ti 및 500 nm Sn을 증착하였다. Ti는 adhesion 향상 및 diffusion barrier 역할을 위해 증착되었다. In과 Sn의 두께는 binary phase diagram을 통해 In-Sn의 eutectic 온도인 $120^{\circ}C$ 지점의 조성 비율인 48 at% Sn과 52 at% In에 해당되는 410 nm (In) 그리고 500 nm (Sn)로 결정되었다. Bonding은 Tbon-100 장비를 이용하여 $140^{\circ}C$, $170^{\circ}C$ 그리고 $200^{\circ}C$에서 2,000 N의 압력으로 진행되었으며 각각의 샘플들은 scanning electron microscope (SEM)을 통해 확인된 후, 접합 강도 테스트를 진행하였다. 추가로 bonding 층의 In 및 Sn 분포를 확인하기 위하여 Si wafer 위에 Ti/In/Sn/Ti를 차례로 증착시킨 뒤 bonding 조건과 같은 온도에서 열처리하고secondary ion mass spectrometry (SIMS) profile 분석을 시행하였다. 결론적으로 본 연구를 통하여 충분히 높은 접합 강도를 갖는 In-Sn eutectic bonding 공정을 $140^{\circ}C$의 낮은 공정온도에서 성공적으로 개발하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.2
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• pp.23-27
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• 1976

$Si{\cdot}SnO_{2}$ heterojunction was prepared by oxidzing at oxygen atmosphere $SnO_{2-X}$ Which made by Flith evaporation of $SnO_{2}$ powder on III surface of p and n type Si single crystals. The energy band Profile of $Si{\cdot}SnO_{2}$ heterojunction was depicted from its physical properties. This heterojunction was very good rectifying junction, very sensitive in spectral response of Photovoltage at from 400nm to 1200nm, and -10$^{18}$sec of time contant. From above properties, this heterojunction was found ps good high speed photovoltaic device and solar cell.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.6
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• pp.95-99
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• 2013

Furnace is currently the most important doping process using POCl3 in solar cell. However furnace need an expensive equipment cost and it has to purge a poisonous gas. Moreover, furnace typically difficult appling for selective emitters. In this study, we developed a new atmospheric pressure plasma source, in this procedure, we research the atmospheric pressure plasma doping that dopant is phosphoric acid($H_3PO_4$). Metal tube injected Ar gas was inputted 5 kV of a low frequency(scores of kHz) induced inverter, so plasma discharged at metal tube. We used the P type silicon wafer of solar cell. We regulated phosphoric acid($H_3PO_4$) concentration on 10% and plasma treatment time is 90 s, 150 s, we experiment that plasma current is 70 mA. We check the doping depth that 287 nm at 90 s and 621 nm at 150 s. We analysis and measurement the doping profile by using SIMS(Secondary Ion Mass Spectroscopy). We calculate and grasp the sheet resistance using conventional sheet resistance formula, so there are 240 Ohm/sq at 90 s and 212 Ohm/sq at 150 s. We analysis oxygen and nitrogen profile of concentration compared with furnace to check the doped defect of atmosphere.

• Journal of Sensor Science and Technology
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• v.23 no.3
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• Journal of the Korean Ceramic Society
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• v.31 no.2
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• pp.227-233
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• 1994

The Bi-Sr-Ca-Cu-O thin films were deposited by RF-magnetron sputtering method on Si(P-111) wafer without a buffer layer and annealed at various temperatures in oxygen atmosphere. The temperature dependence of electrical resistance, the microstructure of intermediate phase, and the surface morphology of films were examined by four probe method, XRD, and SEM, respectively. The chemical composition and the depth profile of the films were determined by ESCA spectra. Thin films annealed at $600^{\circ}C$ and $700^{\circ}C$ in oxygen atmosphere showed onset temperatures of 90 K and 85K, and Tc(zero) of 22K and 31K, respectively. The sample annealed at $700^{\circ}C$ had the highest volume fraction of superconducting phase and showed smooth microsturcture. In ESCA spectra, the thin films were homogeneous with depth.