• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.164-167
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

• 한국진공학회지
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• 제14권2호
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• pp.91-96
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• 2005

양성자 주입과 웨이퍼접합기술을 접목한 ion-cut기술로서 SOI 웨이퍼를 제조하는 기술을 개발하였다. SRIM 전산모사에 의하면 일반 SOI 웨이퍼 (200nm SOI, 400nm BOX) 제조에는 65keV의 양성자주입이 요구된다. 웨이퍼분리를 위한 최적 공정조건을 얻기 위해 조사선량과 열처리조건(온도 및 시간)에 따른 blistering 및 flaking 등의 표면변화를 조사하였다. 실험결과 유효선량범위는 $6\~9times10^{16}H^+/cm^2$이며, 최적 아닐링조건은 $550^{\circ}C$에서 30분 정도로 나타났다. RCA 세정법으로서 친수성표면을 형성하여 웨이퍼 직접접합을 수행하였으며, IR 조사에 의해 무결함접합을 확인하였다 웨이퍼 분리는 예비실험에서 정해진 최적조건에서 이루어졌으며, SOI층의 안정화를 위해 고온열처리($1,100^{\circ}C,\;60$분)를 시행하였다. TEM 측정상 SOI 구조결함은 발견되지 않았으며, BOX(buried oxide)층 상부계면상의 포획전하밀도는 열산화막 계면의 낮은 밀도를 유지함을 확인하였다.

• 한국재료학회지
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• 제12권6호
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.110.3-110
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• 1998

• 한국재료학회지
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• 제12권2호
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.387-390
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for 2 inch SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECVD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using IR camera and SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of $5.3 kgf/cm^2$ to $15.5 kgf/cm^2$

• 한국표면공학회지
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• 제56권3호
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권7호
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• pp.424-432
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• 2000

The plasma surface treatment, using hydrogen gas, of the silicon wafer was investigated as a pretreatment for the application to silicon-on-insulator (SOI) wafers using the silicon direct bonding technique. The chemical reactions of hydrogen plasma with surfaces were used for both the surface activation and the removal of surface contaminants. As a result of exposure of silicon wafer to the plasma, an active oxide layer was formed on the surface, which was rendered hydrophilic. The surface roughness and morphology were estimated as functions of plasma exposing time as well as of power. The surface became smoother with decreased incident hydrogen ion flux by reducing plasma exposing time and power. This process was very effective to reduce the carbon contaminants on the silicon surface, which was responsible for a high initial surface energy. The initial surface energy measured by the crack propagation method was 506 mJ/m2, which was up to about three times higher than that of a conventional RCA cleaning method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1267-1269
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• 1997

본 논문에서는 SDB(Silicon Direct Bonding) 기술을 적용하여 빠른 스위칭 속도 및 낮은 도통 전압을 갖는 1200v 10A n-ch IGBT를 제작하였다. 기존의 epi wafer를 이용한 IGBT 제작시 스위칭 속도 개선을 위한 전자조사 방법을 사용하지 않고 buffer의 농도를 증가시켜 아노드 영역의 정공 주입 효율을 제어하여 90ns의 스위칭 속도를 가지며, 2.0V의 도통전압을 갖는 IGBT를 구현하였으며, SDB IGBT 제작시 bonding 계면의 문제 및 표면의 particle 및 결함이 소자의 전기적 특성에 미치는 영향을 고찰하였으며, 이를 실험 결과와 비교 평가하였다.

• E2M - 전기 전자와 첨단 소재
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• 제8권2호
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• pp.165-170
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• 1995

This paper describes the fabrication and characteristics of a Si Hall sensor fabricated on a SOI (Si-on-insulator) structure. The SOI structure was formed by SDB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall sensor. The Hall voltage and sensitivity of the implemented SDB SOI Hall sensors showed good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall sensor was average 600V/A.T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10.mu.m. Moreover, this sensor can be used at high-temperature, high-radiation and in corrosive environments.