• Journal of Sensor Science and Technology
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• v.13 no.3
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• pp.230-235
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• 2004

This paper describes the design, fabrication and characteristics of a piezoelectric valve using MCA(Multilayer ceramic actuator). The MCA valve, which has the buckling effect, consists of three separate structures; MCA, a valve actuator die and an a seat die. The design of the actuator die was done by FEM modeling and displacement measurement, respectively. The valve seat die with 6 trenches was made, and the actuator die, which is driven to MCA under optimized conditions, was also fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the seat/actuator die structure. PDMS sealing pad was fabricated to minimize a leak-rate. It was also bonded to seat die and SUS package. The MCA valve shows a flow rate of 9.13 seem at a supplied voltage of 100 V with a 50% duty cycle, maximum non-linearity was 2.24% FS and leak rate was $3.03{\times}10^{-8}pa{\codt}m^{3}/cm^{2}$. Therefore, the fabricated MCA valve is suitable for a variety of flow control equipment, a medical bio-system, automobile and air transportation industry.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.515-520
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• 2004

We report on the development of a Piezoelectric valvc that is designed to have a high reliability for fluid control systems, such as mass flow control, transportation and chemical analysis. The valve was fabricated using a MCA(multilayer ceramic actuator), which has a low consumption power, high resolution and accurate control. The fabricated valve is composed of MCA, a valve actuator die and an seat die. The design of the actuator dic was done by FEM(finite element method) modeling, respectively. And, the valve seat die with 6 trenches was made. and the actuator die, which possible to optimize control to MCA, was fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the scat/actuator die structure. PDMS(poly dimethylsiloxane) sealing pad was fabricated to minimize a leak-rate. It was also bonded to scat die and stainless steel package. The flow rate was 9.13 sccm at a supplied voltage of 100 V with a 50 % duty ratio and non-linearity was 2.24 % FS. From these results, the fabricated MCA valve is suitable for a variety of flow control equipments, a medical bio-system, semiconductor fabrication process, automobile and air transportation industry with low cost, batch recess and mass production.

• Journal of the Korean Society for Precision Engineering
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• v.11 no.1
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• pp.150-156
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• 1994

To meet the process requirement of semiconductor device manufacturing, it is necessary to improve the alignment accuracy in exposure equipments. We developed the excimer laser stepper and will describe the methodology for alignment measurement and experimental results. Our wafer alignment system consists of off-axis optics, TTL(Through The Lens) optics and high precision stage. Off-axis alignment utilizes the image processing and /or diffraction from thealign marks of off-centered chip area. On the other hand, TTL alignment can be used for the die-by-die alignment using dual beam interferometry. When only off-axis alignment was used, the experimental alignment error(lml+3 .sigma. ) was 0.26-0.29 .mu. m, and will be reduced down to 0.15 .mu. m by adding TTL alignment.

• Transactions of Materials Processing
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• v.15 no.1 s.82
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• pp.9-14
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• 2006

In the present research, the simultaneous punching of ultra small size hole of $2\~10\;{\mu}m$ in diameter on flat rolled thin metal foils was conducted with elastic polymer punch. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of 1.5fm in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The process set-up is similar to that of the flexible rubber pad farming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions. The effects of the wafer die hole dimension and heat treatment of the workpiece on ultra small size hole formation of the thin foil were discussed. The process condition such as proper die shape, pressure, pressure rate and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole away in a one step operation.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.1-7
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• 2023

Recently, in the semiconductor industry, memory device market is focusing on producing ultra-thin wafers for high integration. In the wafer manufacturing process, wafers after backgrinding and CMP process must be picked up as individual dies and subjected to be peeled off from the dicing tape. However, ultra-thin dies are vulnerable to the possibility of breakage and failure in their thickness and size. This research studies the mechanism of peeling a die with a high-aspect ratio using a thermopneumatic method instead of a die ejector with physical pins. Setting compressed air and the temperature as main factors, we determine the success of the digester using thermopneumatic system and analyze the good die to find the possibility of making mass-production equipment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.913-916
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• 2005

This paper describes the design, fabrication and characteristics of a piezoelectric valve using MCA(Multilayer ceramic actuator). The MCA valve, which has the buckling effect, consists of three separate structures; MCA, a valve actuator die and an a seat die. The design of the actuator die was done by FEM modeling and displacement measurement, respectively. The valve seat die with 6 trenches was made, and the actuator die, which is driven to MCA under optimized conditions, was also fabricated. After Si-wafer direct bonding between the seat die and the actuator die, MCA was also anodic bonded to the seat/actuator die structure. PDMS sealing pad was fabricated to minimize a leak-rate. It was also bonded to seat die and SUS package. The MCA valve shows a flow rate of 9.13 sccm at a supplied voltage of 100 V with a 50 % duty cycle, maximum non-linearity was 2.24 % FS and leak rate was $3.03{\times}10^{-8}pa$. $m^3/cm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.478-480
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• 2004

다이아몬드 톱날을 이용한 얇은 Si 웨이퍼의 기계적인 다이싱은 chipping, crack 등의 문제점을 발생시킨다. 또한 stacked die 나 multi-chip등과 같은 3D-WLP(wafer level package)에서 via를 생성하기 위해 현재 사용되는 화학적 etching은 공정속도가 느리고 제어가 힘들며, 공정이 복잡하다는 문제점을 가지고 있다. 이러한 문제점을 해결하기 위해 현재 연구되고 있는 분야가 레이저를 이용한 웨이퍼 다이싱 및 드릴링이다. 본 논문에서는 UV 레이저를 이용한 얇은 Si 웨이퍼 다이싱 및 드릴링 시스템에 대해 소개하고, 웨이퍼 다이싱 및 드릴링 실험결과를 바탕으로 적절한 레이저 및 공정 매개변수에 대해 설명한다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.