• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.119-124
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• 2021

In a situation where Moore's law, which states that the performance of semiconductor integrated circuits doubles every two years, is showing a limit from a certain point, and it is difficult to increase the performance due to the limitations of exposure technology.In this study, a wafer hybrid method that can increase the degree of integration Various research on bonding technology is currently in progress. In this study, in order to achieve rotational precision between wafers in wafer hybrid bonding technology, modeling of θ_z alignment stage and VCM actuator modeling used for rotational alignment, magnetic field analysis and desgin, control, and evaluation are performed. The system of this study was controlled by VCM actuator, capactive sensor, and dspace, and the working range was ±7200 arcsec, and the in-position and resoultion were ±0.01 arcsec. The results of this study confirmed that safety and precise control are possible, and it is expected to be applied to the process to increase the integration.

• 전자통신동향분석
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• 제36권3호
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• pp.23-33
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• 2021

Two main technologies of III-V/Si laser diode for optical communication, direct epitaxial growth, and wafer bonding were studied. Until now, the wafer bonding has been vigorously studied and seems promising for the ideal III-V/Si laser. However, the wafer bonding process is still complicated and has a limit of mass production. The development of a concise and innovative integration method for silicon photonics is urgent. In the future, the demand for high-speed data processing and energy saving, as well as ultra-high density integration, will increase. Therefore, the study for the hetero-junction, which is that the III-V compound semiconductor is directly grown on Si semiconductor can overcome the current limitations and may be the goal for the ideal III-V/Si laser diode.

• 한국재료학회지
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• 제12권10호
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 1999년도 특별강연 및 추계학술발표대회 개요집
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• pp.247-250
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• 1999

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.81-85
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• 2013

웨이퍼 적층 기술은 반도체 전 후 공정을 이용한 효과적인 방법으로 향후 3D 적층 시스템의 주도적인 발전방향이라고 할 수 있다. 웨이퍼 레벨 3D 적층 시스템을 제조하기 위해서는 TSV (Through Si Via), 웨이퍼 본딩, 그리고 웨이퍼 thinning의 단위공정 개발 및 웨이퍼 warpage, 열적 기계적 신뢰성, 전력전달, 등 시스템적인 요소에 대한 연구개발이 동시에 진행되어야 한다. 본 연구에서는 웨이퍼 본딩에 가장 중요한 역할을 하는 Cu CMP (chemical mechanical polishing) 공정에 대한 특성 분석을 진행하였다. 8인치 Si 웨이퍼에 다마신 공정으로 Cu 범프 웨이퍼를 제작하였고, Cu CMP 공정과 oxide CMP 공정을 이용하여 본딩 층 평탄화에 미치는 영향을 살펴보았다. CMP 공정 후 Cu dishing은 약 $180{\AA}$이었고, 웨이퍼 표면부터 Cu 범프 표면까지의 최종 높이는 약 $2000{\AA}$이었다.

• 대한기계학회논문집A
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• 제25권1호
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• pp.11-15
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• 2001

We present the design and strength evaluation of an anodically bonded pressurized cavity array, based on the energy release rate measured from the anodically bonded plates of two dissimilar materials. From a theoretical analysis, a simple fracture mechanics model of the pressurized cavity array has been developed. The energy release rate (ERR) of the bonded cavity with an infinite bonding length has been derived in terms of cavity pressure, cavity size, bonding length, plate size and material properties. The ERR with a finite bonding length has been evaluated from the finite element analysis performed for varying cavity and plate sizes. It is found that, for an inter-cavity bonding length greater than the half of the cavity length, the bonding strength of cavity array approaches to that of the infinite plate. For a shorter bonding length, however, the bonding strength of the cavity array is monotonically decreased with the ratio of the bonding length to the cavity length. The critical ERR of 6.21J/㎡ has been measured from anodically bonded silicon-glass plates. A set of critical pressure curves has been generated for varying cavity array sizes, and a design method of the pressurized cavity array has been developed for the failure-free wafer-level packaging of MEMS devices.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.277-278
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• 2012

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.71-74
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• 2013

본 연구에서는 웨이퍼 레벨 적층 과정에서 발생하는 웨이퍼 오정렬(misalignment) 현상과 웨이퍼 휘어짐(warpage)과의 관계에 대해서 조사하였다. $0.5{\mu}m$ 두께의 구리 박막 증착을 통해 최대 $45{\mu}m$의 휨 크기(bow height)를 갖는 웨이퍼를 제작하였으며, 이 휘어진 웨이퍼와 일반 웨이퍼를 본딩하였을 때 $6{\sim}15{\mu}m$ 정도의 정렬 오차가 발생하였다. 이는 약 $5{\mu}m$의 웨이퍼 확장(expansion)과 약 $10{\mu}m$의 미끄러짐(slip)의 복합 거동으로 설명할 수 있으며, 웨이퍼 휘어짐의 경우 확장 오정렬보다 본딩 과정에서의 미끄러짐 오정렬에 주로 기여하는 것으로 보인다.

• 센서학회지
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• 제9권2호
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• pp.134-140
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• 2000

Si기판 직접접합기술은 전자소자 및 MEMS에의 응용에 있어 대단히 매력적인 기술이다. 본 논문에서는 Si기판 직접접합에 있어서 HF 전처리 조건에 따른 초기접합에 관하여 서술한다. 접합된 시료들의 특성은 HF 농도, 인가하중과 같이 각각의 접합조건하에서 분석하였으며, 접합력은 인장강도측정법에 의해 평가하였다. 계면상의 결합성분과 표면의 거칠기는 FT-IR과 AFM을 사용하여 평가하였다. HF 전처리 후 Si기판 표면상의 Si-F결합은 DI water에 세정하는 동안 Si-OH로 재배열되며, 결과적으로 hydrophobic 기판은 Si-OH$\cdots$(HOH$\cdots$HOH$\cdots$HOH)$\cdots$OH-S의 수소결합되어 hydrophilic화된다. 초기접합력은 초기접합전의 HF 전처리 조건에 의존한다. (최소 : $2.4kgf/cm^2{\sim}$최대 : $14.9kgf/cm^2$)