• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.164-167
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.9
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• pp.969-975
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• 2009

In this paper, bonded wafer analysis system is proposed using laser beam transmission; while the transmission model is derived by simulation. Since the failure of bonded wafer stems in void existence, transmittance deviations caused by the thickness of the void are analyzed and variations of the intensity through the void or defect easily have been recognized then the testing power has been increased. In addition, large screen display on laser study has been done which resulted in acquiring a feasible technique for analysis of the whole bonding surface. In this regard, three approaches are demonstrated in which Halogen lamp, IR lamp and laser have been tested and subsequently by results comparison the optimized technique using laser has been derived.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.743-746
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• 2000

The removal of contaminants of silicon wafers has been investigated by various methods. Laser cleaning is the new dry cleaning technique to replace wafer wet cleaning in the near future. A dry laser cleaning uses inert gas jet to remove contaminant particles lifted off by the action of a KrF excimer laser. A laser cleaning model is developed to simulate the cleaning process and analyze the influence of contaminant particles and experimental parameters on laser cleaning efficiency. The model demonstrates that various types of submicrometer-sized particles from the front sides of silicon wafer can be efficiently removed by laser cleaning. The laser cleaning is explained by a particle adhesion model. including van der Waals forces and hydrogen bonding, and a particle removal model involving rapid thermal expansion of the substrate due to the thermoelastic effect. In addition, the experiment of wafer laser cleaning using KrF excimer laser was conducted to remove various contaminant particles.

• Korean Journal of Materials Research
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• v.10 no.10
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• pp.665-670
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• 2000

Linear annealing method was developed to increase the bond strength of Si wafer pair mated at room tem­perature instead of conventional furnace annealing method. It has been known that the interval of the two mating wafer surfaces decreases and the density of gaseous phases generated at the interface increases with increase in an-nealing temperature. The new annealing method consisting of one heat source and light reflecting mirror used these two phenomena and was applied to Si$\mid$$\mid$Si and Si$\mid$$\mid$$SiO_2/Si$ bonding. The bonding interface observed directly by using IR camera and HRTEM showed clear bonding interface without any unbonded areas except the area generated by the dusts inserted into the mating interface at the room temperature. Crack opening method and direct tensile test was ap­pplied to measure the bond strength. The two methods showed similar results. The bond strength increased continuous­tly with the increase of annealing temperature.

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.52-55
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• 2016

GZO film was prepared on p-type Si wafer and then annealed at various temperatures in an air conditions to research the bonding structures in accordance with the annealing processes. GZO film annealed in an atmosphere showed the various bonding structure depending on annealing temperatures and oxygen gas flow rate during the deposition. The difference of bonding structures of GZO films made by oxygen gas flows between 18 sccm and 22 sccm was so great. The bonding structures of GZO films made by oxygen gas flow of 18 sccm were showed the crystal structure, but that of 22 sccm were showed the amorphous structure in spite of after annealing processes. The bonding structure of GZO as oxide-semiconductor was observed the trend of becoming amorphous structures at the temperature of $200^{\circ}C$. Therefore, the characteristics of oxide semiconductor are needed to research the variation near the annealing at $200^{\circ}C$.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Journal of Power System Engineering
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• v.5 no.4
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.86-89
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• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.