• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.5
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.763-770
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• 1996

In this paper, the Single-stage Transmission type Injectiong-Locked Oscillator(STILO) was designed and fabicated for the Active Integrated Phased Array Antenna(AIPAA) system. The STILO, which was designed and fabricated by injection-locked technique and hair-pin resonator, has the same 210MHz frequency tuning range of the Voltage Controlled Oscillator(VCO) used by varactor. The locking bandwidth of STILO with 11.5MHz bandwidth, is much better than that of the Injection-Locked Dielectric Resonator Oscillator(ILDRO), And the STILO has the improved noise characteristics in AM, FM, and PM. This STILO is useful for the AIPAA, the coupled VCO array, an the MMIC structure.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.83-89
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• 2014

A ku-band complementary cross-coupled differential voltage controlled oscillator is designed, measured and fabricated using $0.18-{\mu}m$ CMOS technology. A 2.4GHz of very wide frequency tuning at oscillating frequency of 14.5GHz is achieved with presented circuit topology and MOS varactors. Measurement results show -1.66dBm output power with 18mA DC current drive from 3.3V power supply. When 5V is applied, the output power is increased to 0.84dBm with 47mA DC current. -74.5dBc/Hz phase noise at 100kHz offset is measured. The die area is $1.02mm{\times}0.66mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.311-320
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• 2008

In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.207-212
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• 2012

In this work, a 70/140 GHz dual-band push-push voltage controlled oscillator(VCO) has been developed based on a 0.18-${\mu}m$ SiGe BiCMOS technology. The lower band and the upper band oscillation frequency varied from 67.9 GHz to 76.9 GHz and from 134.3 GHz to 154.5 GHz, respectively, with tuning voltage swept from 0.2 to 2 V. The calibrated maximum output power for each band was -0.55 dBm and -15.45 dBm. The VCO draws DC current of 18 mA from 4 V supply.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.