• Journal of electromagnetic engineering and science
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• v.9 no.3
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• pp.130-140
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• 2009

The design theory and experimental results of a true random noise radar system are presented in this paper. Target range information can be extracted precisely by correlation processing between the delayed reference and the signal received from a target, and the velocity information by the Doppler processing with successive correlation data. A K-band noise radar system was designed using random FM noise signal, and the characteristics of the fabricated system were examined with laboratory and outdoor experiments. A C-band random FM noise signal was generated by applying a low-frequency white Gaussian noise source to VCO(Voltage Controlled Oscillator), and a K-band Tx noise signal with 100 MHz bandwidth was obtained by using a following frequency multiplier. Two modified wave-guide horn arrays were designed and fabricated, and used for the Tx and Rx antennas. The required amount of Tx/Rx isolation was attained by using a coupling cancellation circuit as well as keeping them apart with predetermined spacing. A double down-conversion scheme was used in the Rx and reference channels, respectively, for easy post processing such as correlation and Doppler processing. The implemented noise radar performance was examined with a moving bicycle and a very high-speed target with a velocity of 150 m/s. The results extracted by the Matlab simulation using the logging data were found to be in a reasonable agreement with the expected results.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of Navigation and Port Research
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• v.28 no.6
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• pp.497-501
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• 2004

In this paper, it is presented a level sensor for measuring a level of the contents of cargo tank using frequency modulated continuous wave(FMCW). The frequency range is 10∼11 GHz, the radar cross section(RCS) of test target is $0.8\textrm{m}^2$ of metal plate. The experiment is performed in laboratory and open ground, the sweep time of the signal is 100 ms, the pyramidal horn antenna of about 22 dBi gain is used, and input power of antenna is about 8 dBm The beat frequency according to the target moving to 40 m is measured. There is a good agreement between measured and calculated results. But the resolution of the FMCW radar is measured about 10 cm due to nonlinear of voltage controlled oscillator(VCO).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.107-114
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• 2020

A power amplifier of 2.4 GHz ISM band is designed to implement a transmitter system. High efficiency amplifiers can be implemented as class E or class F amplifiers. This study has designed a 20 W high efficiency class E amplifier that has simple circuit structure in order to utilize for the ISM band application. The impedance matching circuit was designed by class E design theory and circuit simulation. The designed amplifier has the output power of 44.2 dBm and the power added efficiency of 69% at 2.45 GHz. In order to apply 30 dBm input power to the designed power amplifier, voltage controlled oscillator (VCO) and driving amplifier have been fabricated for the input feeding circuit. The measurement of the power amplifier shows 43.2 dBm output and 65% power added efficiency. This study can be applied to the design of power amplifiers for various wireless communication systems such as wireless power transfer, radio jamming device and high power transmitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.208-217
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• 2010

This paper presents a novel 10 GHz bio-radar system based on a frequency multiplier and phase-locked loop(PLL) for non-contact measurement of heartbeat and respiration rates. In this paper, a 2.5 GHz voltage controlled oscillator (VCO) with PLL is employed to as a frequency synthesizer, and 10 GHz continuous wave(CW) signal is generated by using frequency multiplier from 2.5 GHz signal. This paper also presents the noise characteristic of the proposed system. As a result, a better performance and economical frequency synthesizer can be achieved with the proposed bio-radar system. The experimental results shows excellent bio-signal measurement up to 100 cm without any additional digital signal processing(DSP), and the proposed system is validated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.961-966
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• 2009

In this paper, a novel voltage-controlled oscillator(VCO) using the metamaterial broadside coupled spiral resonators(BC-DSRs) is presented for reducing the phase noise. For reducing of the phase noise, the series spiral structures have been applied for the signal plane and ground plane at each in order to have the large coupling. Compared with the conventional VCO, the proposed VCO has the larger coupling coefficient constant, which makes a higher Q-factor and has reduced the phase noise of the VCO. The proposed VCO has the phase noise of $-121{\sim}-117.16\;dBc$/Hz at 100 kHz in the tuning range, $5.749{\sim}5.853\;GHz$. The figure of merit(FOM) of this VCO is $-198.45{\sim}-194.77\;dBc$/Hz at 100 Hz in the same tuning range, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.