• 제목/요약/키워드: Voltage phase

검색결과 4,304건 처리시간 0.037초

대기압 이상의 열처리 공정압력이 Cu2ZnSn(S,Se)4(CZTSSe) 박막 성장에 미치는 영향 (Effect of Annealing Process Pressure Over Atmospheric Pressure on Cu2ZnSn(S,Se)4 Thin Film Growth)

  • 이병훈;류혜선;장준성;이인재;김지훈;조은애;김진혁
    • 한국재료학회지
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    • 제29권9호
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    • pp.553-558
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    • 2019
  • $Cu_2ZnSn(S,Se)_4(CZTSSe)$ thin film solar cells areone of the most promising candidates for photovoltaic devices due to their earth-abundant composition, high absorption coefficient and appropriate band gap. The sputtering process is the main challenge to achieving high efficiency of CZTSSe solar cells for industrialization. In this study, we fabricated CZTSSe absorbers on Mo coated soda lime glass using different pressures during the annealing process. As an environmental strategy, the annealing process is performed with S and Se powder, without any toxic $H_2Se$ and/or $H_2S$ gases. Because CZTSSe thin films have a very narrow stable phase region, it is important to control the condition of the annealing process to achieve high efficiency of the solar cell. To identify the effect of process pressure during the sulfo-selenization, we experiment with varying initial pressure from 600 Torr to 800 Torr. We fabricate a CZTSSe thin film solar cell with 8.24 % efficiency, with 435 mV for open circuit voltage($V_{OC}$) and $36.98mA/cm^2$ for short circuit current density($J_{SC}$), under a highest process pressure of 800 Torr.

DSP와 라즈베리 파이를 기반으로 한 스마트 그리드 전력설비의 통신제어장치 설계 방법론 (Design Methodology of Communication & Control Device for Smart Grid Power Facility based on DSP and Raspberry Pi)

  • 오세영;이준혁;이세인;박창수;고윤석
    • 한국전자통신학회논문지
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    • 제16권5호
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    • pp.835-844
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    • 2021
  • 본 논문에서는 스마트 그리드 전력설비 간 통신을 통해 고장구간을 자율적으로 판단, 분리하기 위한 기반기술인 통신제어장치를 설계하였다. 통신제어장치에서 제어모듈은 3상 전압, 전류를 계측할 수 있도록 DSP, 통신모듈은 전력설비 간 통신을 통해 고장구간을 판단, 고장구간 분리를 실현할 수 있도록 라즈베리 파이로 설계되었다. DSP와 라즈베리 간 통신은 SPI 통신방식을 기반으로, 반면에 라즈베리 간 통신은 Wi-Fi 기반으로 설계되었다. 끝으로, 3개의 전력설비 통신제어 장치로 구성되는 성능 평가 시스템을 구축하였으며, 선로 상의 다양한 고장 이벤트들에 대한 모의 검증을 실시하였다. 평가 결과, 모든 시험경우들에 대해서 통신제어장치가 요구된 응답을 보임으로서 통신제어장치 설계 방법론의 유효성을 확인할 수 있었다.

The characteristic of Cu2ZnSnS4 thin film solar cells prepared by sputtering CuSn and CuZn alloy targets

  • Lu, Yilei;Wang, Shurong;Ma, Xun;Xu, Xin;Yang, Shuai;Li, Yaobin;Tang, Zhen
    • Current Applied Physics
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    • 제18권12호
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    • pp.1571-1576
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    • 2018
  • Recent study shows that the main reason for limiting CZTS device performance lies in the low open circuit voltage, and crucial factor that could affect the $V_{oc}$ is secondary phases like ZnS existing in absorber layer and its interfaces. In this work, the $Cu_2ZnSnS_4$ thin film solar cells were prepared by sputtering CuSn and CuZn alloy targets. Through tuning the Zn/Sn ratios of the CZTS thin films, the crystal structure, morphology, chemical composition and phase purity of CZTS thin films were characterized by X-Ray Diffraction (XRD), scanning electron microscopy (SEM) equipped with an energy dispersive spectrometer (EDS) and Raman spectroscopy. The statistics data show that the CZTS solar cell with a ratio of Zn/Sn = 1.2 have the best power convention efficiency of 5.07%. After HCl etching process, the CZTS thin film solar cell with the highest efficiency 5.41% was obtained, which demonstrated that CZTS film solar cells with high efficiency could be developed by sputtering CuSn and CuZn alloy targets.

Cu2ZnSn(S,Se)4(CZTSSe) 흡수층의 급속 열처리 공정 온도 미세 조절을 통한 특성 향상 (Improvement in Performance of Cu2ZnSn(S,Se)4 Absorber Layer with Fine Temperature Control in Rapid Thermal Annealing System)

  • 김동명;장준성;비제이 가라데;김진혁
    • 한국재료학회지
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    • 제31권11호
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    • pp.619-625
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    • 2021
  • Cu2ZnSn(S,Se)4 (CZTSSe) based thin-film solar cells have attracted growing attention because of their earth-abundant and non-toxic elements. However, because of their large open-circuit voltage (Voc)-deficit, CZTSSe solar cells exhibit poor device performance compared to well-established Cu(In,Ga)(S,Se)2 (CIGS) and CdTe based solar cells. One of the main causes of this large Voc-deficit is poor absorber properties for example, high band tailing properties, defects, secondary phases, carrier recombination, etc. In particular, the fabrication of absorbers using physical methods results in poor surface morphology, such as pin-holes and voids. To overcome this problem and form large and homogeneous CZTSSe grains, CZTSSe based absorber layers are prepared by a sputtering technique with different RTA conditions. The temperature is varied from 510 ℃ to 540 ℃ during the rapid thermal annealing (RTA) process. Further, CZTSSe thin films are examined with X-ray diffraction, X-ray fluorescence, Raman spectroscopy, IPCE, Energy dispersive spectroscopy and Scanning electron microscopy techniques. The present work shows that Cu-based secondary phase formation can be suppressed in the CZTSSe absorber layer at an optimum RTA condition.

가정용 리튬배터리 ESS를 고려한 태양광 발전 하이브리드 PCS 특성에 관한 연구 (A Study on Characteristic of Hybrid PCS for Solar Power Generation Considering on a Residential Lithium Battery ESS.)

  • 황락훈;나승권;최병상
    • 한국항행학회논문지
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    • 제26권1호
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    • pp.35-45
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    • 2022
  • 본 논문에서는 PV 시스템에서 태양광 발전 시스템의 완전한 동작을 위해 DC-DC 벅-부스트 컨버터와 MPPT (Maximum Power Point Tracking)제어 시스템에 대한 완전한 동작 시스템에 대해 모델링하고 시뮬레이션을 수행하여 양호한 동작을 확인하고자 한다. 이를 위해 이중층 커패시터(EDLC:Electric double-layer capacitors )를 사용한 순간전압강하 보상장치가 개발되어 적용되고 있다. 따라서 태양광 발전의 ESS(Energy Storage System)를 고려한 PCS(Power Conditioning System)를 제안하여 부하평준화를 통한 전력의 안정적인 공급을 확인한다. 본 논문에서는 순간전압강하 보상장치(DVR :Dynamic Voltage Restorer)에 사용되는 전기 이중층 커패시터에 비해 동일 사이즈 대비 에너지 밀도가 높은 하이브리드 커패시터(hybrid capacitor)를 적용하는 연구를 하였고, 단상 3[kW] 계통 연계형 태양광 전력변환기를 제안하였다.

LPDDR2 메모리 컨트롤러를 위한 830-Mb/s/pin 송수신기 칩 구현 (Chip Implementation of 830-Mb/s/pin Transceiver for LPDDR2 Memory Controller)

  • 이종혁;송창민;장영찬
    • 전기전자학회논문지
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    • 제26권4호
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    • pp.659-670
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    • 2022
  • 본 논문에서는 ×32 LPDDR2 메모리를 지원하는 컨트롤러를 위한 830-Mb/s/pin 송수신기가 설계된다. 여덟 개의 단위 회로로 구성된 송신단은 34Ω ∽ 240Ω 범위의 임피던스를 가지고 임피던스 보정 회로에 의해 제어된다. 송신되는 DQS의 신호는 DQ의 신호들 대비 90° 이동된 위상을 가진다. 수신 동작시 read time 보정은 바이트 내에서 per-pin 스큐 보정과 클록-도메인 전환을 통해 수행된다. 구현된 LPDDR2 메모리 컨트롤러를 위한 송수신기는 1.2V 공급 전압을 사용하는 55-nm 공정에서 설계되었으며 830-Mb/s/pin의 신호 전송률을 가진다. 각 lane의 면적과 전력 소모는 각각 0.664 mm2과 22.3 mW이다.

Electrochemical Impedance Characteristics of a Low-Temperature Single Cell for CO2/H2O Co-Reduction to Produce Syngas (CO+H2)

  • Min Gwan, Ha;Donghoon, Shin;Jeawoo, Jung;Emilio, Audasso;Juhun, Song;Yong-Tae, Kim;Hee-Young, Park;Hyun S., Park;Youngseung, Na;Jong Hyun, Jang
    • Journal of Electrochemical Science and Technology
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    • 제13권4호
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    • pp.462-471
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    • 2022
  • In this study, the electrochemical impedance characteristics of CO2/H2O co-reduction to produce CO/H2 syngas were investigated in a low-temperature single cell. The effect of the operating conditions on the single-cell performance was evaluated at different feed concentrations and cell voltages, and the corresponding electrochemical impedance spectroscopy (EIS) data were collected and analyzed. The Nyquist plots exhibited two semicircles with separated characteristic frequencies of approximately 1 kHz and tens of Hz. The high-frequency semicircles, which depend only on the catholyte concentration, could be correlated to the charge transfer processes in competitive CO2 reduction and hydrogen evolution reactions at the cathodes. The EIS characteristics of the CO2/H2O co-reduction single cell could be explained by the equivalent circuit suggested in this study. In this circuit, the cathodic mass transfer and anodic charge transfer processes are collectively represented by a parallel combination of resistance and a constant phase element to show low-frequency semicircles. Through nonlinear fitting using the equivalent circuit, the parameters for each electrochemical element, such as polarization resistances for high- and low-frequency processes, could be quantified as functions of feed concentration and cell voltage.

에틸벤젠을 이용한 실리콘 산화물 음극재의 효과적인 카본 코팅 전략 (Effective problem mitigation strategy of lithium secondary battery silicon anode utilized liquid precursor)

  • 이상렬;박성수;채수종
    • 한국표면공학회지
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    • 제56권1호
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    • pp.62-68
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    • 2023
  • Silicon (Si) is considered as a promising substitute for the conventional graphite due to its high theoretical specific capacity (3579 mAh/g, Li15Si4) and proper working voltage (~0.3V vs Li+/Li). However, the large volume change of Si during (de)lithiation brings about severe degradation of battery performances, rendering it difficult to be applied in the practical battery directly. As a one feasible candidate of industrial Si anode, silicon monoxide (SiOx) demonstrates great electrochemical stability with its specialized strategy, downsized Si nanocrystallites surrounded by Li+ inactive buffer phase (Li2O and Li4SiO4). Nevertheless, SiOx inherently has the initial irreversible capacity and poor electrical conductivity. To overcome those issues, conformal carbon coating has been performed on SiOx utilizing ethylbenzene as the carbon precursor of chemical vapor deposition (CVD). Through various characterizations, it is confirmed that the carbon is homogeneously coated on the surface of SiOx. Accordingly, the carbon-coated SiOx from CVD using ethylbenzene demonstrates 73% of the first cycle efficiency and great cycle life (88.1% capacity retention at 50th cycle). This work provides a promising synthetic route of the uniform and scalable carbon coating on Si anode for high-energy density.

Structural Behavior of Mixed $LiMn_2O_4-LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ Cathode in Li-ion Cells during Electrochemical Cycling

  • 윤원섭;이상우
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2011년도 춘계학술발표대회
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    • pp.5-5
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    • 2011
  • The research and development of hybrid electric vehicle (HEV), plug-in hybrid electric vehicle (PHEV) and electric vehicle (EV) are intensified due to the energy crisis and environmental concerns. In order to meet the challenging requirements of powering HEV, PHEV and EV, the current lithium battery technology needs to be significantly improved in terms of the cost, safety, power and energy density, as well as the calendar and cycle life. One new technology being developed is the utilization of composite cathode by mixing two different types of insertion compounds [e.g., spinel $LiMn_2O_4$ and layered $LiMO_2$ (M=Ni, Co, and Mn)]. Recently, some studies on mixing two different types of cathode materials to make a composite cathode have been reported, which were aimed at reducing cost and improving self-discharge. Numata et al. reported that when stored in a sealed can together with electrolyte at $80^{\circ}C$ for 10 days, the concentrations of both HF and $Mn^{2+}$ were lower in the can containing $LiMn_2O_4$ blended with $LiNi_{0.8}Co_{0.2}O_2$ than that containing $LiMn_2O_4$ only. That reports clearly showed that this blending technique can prevent the decline in capacity caused by cycling or storage at elevated temperatures. However, not much work has been reported on the charge-discharge characteristics and related structural phase transitions for these composite cathodes. In this presentation, we will report our in situ x-ray diffraction studies on this mixed composite cathode material during charge-discharge cycling. The mixed cathodes were incorporated into in situ XRD cells with a Li foil anode, a Celgard separator, and a 1M $LiPF_6$ electrolyte in a 1 : 1 EC : DMC solvent (LP 30 from EM Industries, Inc.). For in situ XRD cell, Mylar windows were used as has been described in detail elsewhere. All of these in situ XRD spectra were collected on beam line X18A at National Synchrotron Light Source (NSLS) at Brookhaven National Laboratory using two different detectors. One is a conventional scintillation detector with data collection at 0.02 degree in two theta angle for each step. The other is a wide angle position sensitive detector (PSD). The wavelengths used were 1.1950 ${\AA}$ for the scintillation detector and 0.9999 A for the PSD. The newly installed PSD at beam line X18A of NSLS can collect XRD patterns as short as a few minutes covering $90^{\circ}$ of two theta angles simultaneously with good signal to noise ratio. It significantly reduced the data collection time for each scan, giving us a great advantage in studying the phase transition in real time. The two theta angles of all the XRD spectra presented in this paper have been recalculated and converted to corresponding angles for ${\lambda}=1.54\;{\AA}$, which is the wavelength of conventional x-ray tube source with Cu-$k{\alpha}$ radiation, for easy comparison with data in other literatures. The structural changes of the composite cathode made by mixing spinel $LiMn_2O_4$ and layered $Li-Ni_{1/3}Co_{1/3}Mn_{1/3}O_2$ in 1 : 1 wt% in both Li-half and Li-ion cells during charge/discharge are studied by in situ XRD. During the first charge up to ~5.2 V vs. $Li/Li^+$, the in situ XRD spectra for the composite cathode in the Li-half cell track the structural changes of each component. At the early stage of charge, the lithium extraction takes place in the $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ component only. When the cell voltage reaches at ~4.0 V vs. $Li/Li^+$, lithium extraction from the spinel $LiMn_2O_4$ component starts and becomes the major contributor for the cell capacity due to the higher rate capability of $LiMn_2O_4$. When the voltage passed 4.3 V, the major structural changes are from the $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ component, while the $LiMn_2O_4$ component is almost unchanged. In the Li-ion cell using a MCMB anode and a composite cathode cycled between 2.5 V and 4.2 V, the structural changes are dominated by the spinel $LiMn_2O_4$ component, with much less changes in the layered $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ component, comparing with the Li-half cell results. These results give us valuable information about the structural changes relating to the contributions of each individual component to the cell capacity at certain charge/discharge state, which are helpful in designing and optimizing the composite cathode using spinel- and layered-type materials for Li-ion battery research. More detailed discussion will be presented at the meeting.

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높은 정확도를 가진 집적 커페시터 기반의 10비트 250MS/s $1.8mm^2$ 85mW 0.13un CMOS A/D 변환기 (A 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS ADC Based on High-Accuracy Integrated Capacitors)

  • 사두환;최희철;김영록;이승훈
    • 대한전자공학회논문지SD
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    • 제43권11호
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    • pp.58-68
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    • 2006
  • 본 논문에서는 차세대 디지털 TV 및 무선 랜 등과 같이 고속에서 저전압, 저전력 및 소면적을 동시에 요구하는 고성능 집적시스템을 위한 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D 변환기 (ADC)를 제안한다. 제안하는 ADC는 요구되는 10b 해상도에서 250MS/s의 아주 빠른 속도 사양을 만족시키면서, 면적 및 전력 소모를 최소화하기 위해 3단 파이프라인 구조를 사용하였다. 입력단 SHA 회로는 게이트-부트스트래핑 (gate-bootstrapping) 기법을 적용한 샘플링 스위치 혹은 CMOS 샘플링스위치 등 어떤 형태를 사용할 경우에도 10비트 이상의 해상도를 유지하도록 하였으며, SHA 및 두개의 MDAC에 사용되는 증폭기는 트랜스컨덕턴스 비율을 적절히 조정한 2단 증폭기를 사용함으로써 10비트에서 요구되는 DC 전압 이득과 250MS/s에서 요구되는 대역폭을 얻음과 동시에 필요한 위상 여유를 갖도록 하였다. 또한, 2개의 MDAC의 커패시터 열에는 소자 부정합에 의한 영향을 최소화하기 위해서 인접신호에 덜 민감한 향상된 3차원 완전 대칭 구조의 커패시터 레이아웃 기법을 제안하였으며, 기준 전류 및 전압 발생기는 온-칩 RC 필터를 사용하여 잡음을 최소화하고, 필요시 선택적으로 다른 크기의 기준 전압을 외부에서 인가할 수 있도록 설계하였다. 제안하는 시제품 ADC는 0.13um 1P8M CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 각각 최대 0.24LSB, 0.35LSB 수준을 보여준다. 또한, 동적 성능으로는 200MS/s와 250MS/s의 동작 속도에서 각각 최대 54dB, 48dB의 SNDR과 67dB, 61dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 $1.8mm^2$이며 전력 소모는 1.2V 전원 전압에서 최대 동작 속도인 250MS/s일 때 85mW이다.