• The Journal of the Acoustical Society of Korea
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• v.28 no.2
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• pp.119-126
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• 2009

This paper describes the non-stringed guitar composed of laser strings, frets, sound synthesis algorithm and a processor. The laser strings that can depict stroke and playing arpeggios comprise laser modules and photo diodes. Frets are implemented by voltage divider. The guitar body does not need to implement physically because commuted waveguide synthesis is used. The proposed frets enable; players to represent all of chords by the chord glove as well as guitar solo. Sliding, hammering-on and pulling-off sounds are synthesized by using parameters from the voltage divider. Because the pitch shifting corresponds to the time-varying propagation speed in the digital waveguide model, the proposed model can synthesize vibrato as well. After transformation of signals from the laser strings and frets into parameters for synthesis algorithm, the digital signal processor, TMS320F2812, performs the real-time synthesis algorithm and communicates with the DAC. The demonstration movieclip available via the Internet shows one to play a song, 'Arirang', synthesized by proposed algorithm and interfaces in real-time. Consequently, we can conclude that the proposed synthesis algorithm is efficient in guitar solo and there is no problem to play the non-stringed guitar in real-time.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.831-833
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• 2004

A novel transflective-type LC mode with good display performance has been developed In order to drive both transmissive and reflective modes simultaneously without any modulation of gamma in a single-gap structure, we have introduced a new design concept in the reflective region, where the capacitance is separated into liquid crystal($C_{LC}$} and organic layer($C_{OL}$), playing a key role as a voltage divider in our cap-divided VA-mode. With this cap-divided method having both merits of simplifying process and good legibility, we have achieved good optical characteristics such as high contrast ratio and wide viewing angle in a single-gap homeotropic panel design.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.950-955
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• 2013

This paper proposes a new low-cost current detection method to implement vector-controlled inverter of 3-phase induction motor or permanent-magnet synchronous motor using 2 shunt resistors instead of expensive Hall current sensors. The proposed method can detect perfect phase currents without current-immeasurable area in all operating conditions of motor. This method uses 2 shunt resistors in Hall current sensor positions conventionally used to detect phase currents. Therefore, it requires accurate analog differential amplifiers to detect voltages across shunt resistors at high electric potential to ground. We show the good solutions which are implemented by voltage-divider resistors networks and the instrumentation amplifiers using several Op Amps at cheap price. Computer simulations and experiments were performed to confirm the effectiveness of proposed method. These results show that proposed method can perfectly detect phase currents without current-immeasurable area in all operating conditions of motor.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.27 no.2
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• pp.310-316
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• 2003

One of the significant subject in the automatic arc welding is to establish control system of the welding parameters for controlling bead geometry as a criterion to evaluate the quality of arc welding. This paper proposes an inference algorithm for bead geometry in CMA Welding using Neuro-Fuzzy algorithm. The characteristic welding parameters are measured by the circuit composed of hall sensor, voltage divider tachometer, etc. and then the bead geometry of each weld pool is calculated and detected by an image processing with CCD camera and a measuring with microscope. The relationships between the characteristic welding parameters and the bead geometry have been arranged empirically. From the result of experiments, membership functions and fuzzy rules are tuned and determined by the learning of neural network, and then the relationship between actual bead geometry and inferred bead geometry are concluded by fuzzy logic controller. In the applied inference system of bead geometry using Neuro-Fuzzy algorithm, the inference error percent is within -5%∼+4% in case of bead width, -10%∼+10% in bead height, -5%∼+6% in bead area, -10%∼+10% in penetration. Use of the Neuro-Fuzzy algorithm allows the CMA Welding system to evaluate the quality in bead geometry in real time as the welding parameters change.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.509-510
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• 2006

전류 및 전압을 측정하는 것은 오래전부터 CT(current transformer)/PT(potential transformer) 가 많이 사용되어져 왔지만, 이들은 iron core를 사용하기 때문에 포화특성이 발생하게 되어, 오차를 유발하게 된다. 이에 대한 대처 방안으로서 현재는 로고스키코일 및 분압방식을 이용한 ECT/EVT에 대한 적용이 진행이 되고 있다. ECT/EVT는 포화특성이 없고, 선형성이 매우우수하며, 소형, 경량이라는 점에서 현재 배전반의 변화 추세를 구현할 수 있는 충분한 능력을 지니고 있다. 이에 본 논문에서는 ECT/EVT를 제작하여, 특성을 분석하고자 한다. 특이점은 ECT/EVT가 EPOXY SPACER에 내장이 되어 사용이 되며, 이런 사용조건하에서의 이들의 특성이 변화 될 수 있는지를 살펴보았다. 그 결과 EPXOY 몰딩하에서도 그 선형성을 잃지 않았으며, 원하는 오차인 ${\pm}1%$에 부합되는 결과를 나타내었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.665-667
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• 2010

In this paper, the method to detect the IM(Inter Modulation) components of power amplifier is proposed by using frequency down-convertor. Output signals of power amplifier which is coupled by 20dB coupler and divided by power divider are applied to RF and LO of the frequency converter. It could be found the magnitude of IM components of power amplifier as a converted DC voltage which is come from the difference between 3th and 5th IM component. The detected DC voltage values are changed from 0.72V to 0.9V when 3rd IM component level changed from -26.4dBm to +2.15dBm and 5th IM component level changed from -34.2dBm to -12.89dBm as the Vgs of 3W power amplifier is changed.