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Design of a 960MHz CMOS PLL Frequency Synthesizer with Quadrature LC VCO  

Kim, Shin-Woong (Department of Information Communication Engineering, Handong Global University)
Kim, Young-Sik (Department of Information Communication Engineering, Handong Global University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.7, 2009 , pp. 61-67 More about this Journal
Abstract
This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.
Keywords
PLL; VCO; Integer-N; Phase noise; Frequency synthesise;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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