• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1985-1991
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• 1999

In this paper, complete and general two-port lumped Spice-network model is developed for a lossy transmission line. This model is realized as a Spice subcircuit, by means of standard lumped network elements and mathematical functions. It is used as a component in the time-domain simulation of a high-speed data transmission line such as IMI(Inter Module Interface) data path in HANbit ACE 64 ATM switching system. The only required Spice network elements are resistance and frequency-dependent controlled-voltage sources. Such frequency-dependent sources are realized by utilizing the standard Hspice mathematical functions FREQ, DELAY, and POLY.

• Journal of IKEEE
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• v.15 no.1
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.275-284
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• 2004

This paper discusses how to control the compensation voltages in dynamic voltage restorers (DVR). On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. Based on the preceded power stage analysis, a novel controller for the compensation voltages of DVRs is proposed by a feed forward control scheme. This paper discusses also the time delay problems in the control system of DVRs. Digitally controlled DVR systems normally have control delay at amount of one sampling time of the control system and a half of the switching period of the DVR inverter. The control delay in digital controllers increases the dimension of the system transfer function one degree higher, which makes the control system more complicate and more unstable. This paper proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs with digital controllers. Proposed theory is verified by an experimental DVR system with a full digital controller.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.2
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• pp.41-46
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• 2019

The application of series compensator in a power system affects other devices such as circuit breakers transient recovery voltage (TRV) problem. In this paper, we analyze the TRV effect on a line circuit breaker in the cases with and without thyristor-controlled series capacitor (TCSC) via simulation, and suggest an effective method to overcome the increase of TRV due to the TCSC installation. It also discusses the impact of proposed protection on metal oxide varistor (MOV). A 345 kV transmission line in Korea was selected as a study case. Grid system was modelled using PSCAD (Power Systems Computer Aided Design) / EMTDC(Electro Magnetic Transient Direct Current). The TRV was analyzed by implementing a short circuit fault along the transmission line and at the breaker terminal. The proposed protection scheme, the TRV satisfies the standard. However, the MOV energy capacity increased as the delay time increased. This result can solve the TRV problem caused by the expected transmission line fault in a practical power system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.67-75
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• 1998

This paper examined the geometrical variables of microstrip to control the characteristic impedance of MCM interconnect and also with respect to the practical requirements, evaluated the critical lengths for attenuation, propagation delay, and crosstalk at 500 MHz frequency compared to at 50 MHz frequency. With the illustration of each MCM-L and MCM-D interconnect having 50 characteristic impedance, it was revealed that the most important geometrical variables to control the characteristic impedance of microstrip are eventually dielectric thickness and line width. In particular, the dielectric thickness of MCM-D interconnect must be controlled with tolerance below 2 m. It is clear that the attenuation does not give rise to signal distortion in the range of up to 500MHz frequency for both MCM-L and MCM-D interconnects. However, the propagation delay is so significant that both MCM-L and MCM-D interconnects should be matched with load at the 500 MHz frequency. For the MCM-D interconnect, the crosstalk voltage would not be high to generate the wrong signal on the neighboring line at 500 MHz frequency, but the MCM-L interconnect could not be used due to severe crosstalk. Eventually, it is clear that the transmission line behavior must be studied for the design of MCM substrate at the 500 MHz frequency.