• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.265-269
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• 2008

Output voltage value of AC high voltage source has usually been obtained by measuring the low arm voltage of high voltage divider or the secondary voltage of high voltage transformer. In this study, we have fabricated the AC 400 kV high voltage divider using high voltage electrode and electric field measurement sensor. The dividing ratio of the fabricated 400 kV high voltage divider was evaluated using reference 400 kV capacitive divider. The dividing ratio of 400 kV high voltage divider is found to be 12,322 and has the good linearity within 0.63 % against AC high voltage up to 400 kV. Therefore, the developed 400 kV high voltage divider could evaluate 400 kV high voltage supply and voltage divider used in industry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.11
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• pp.681-684
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• 2016

This research was carried out experiments of variety IGBTs for industrial inverter and electric vehicle. The devices for this paper were planar gate IGBT, trench gate IGBT and dual gate IGBT and we designed using same design and process parameters. As a result of experiments, the electrical characteristics of planar gate IGBT were 1,459 V of breakdown voltage, 4.04 V of threshold voltage and 4.7 V of on-state voltage drop. And the electrical characteristics of trench gate IGBT were 1,473 V of breakdown voltage, 4.11 V of threshold voltage and 3.17 V of on-state voltage drop. Lastly, the electrical characteristics of dual gate IGBT were 1,467 V of breakdown voltage, 4.14 V of threshold voltage and 3.08V of on-state voltage drop. We almost knew that the trench gate IGBT was superior to dual gate IGBT in terms of breakdown voltage. On the other hand, the dual gate IGBT was better than the trench gate IGBT in terms of on state voltage drop.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.11
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.323-324
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• 2019

For flash memory devices with Ge-MONOS(metal-Oxide-Nitride-Oxide-Silicon) structures, variations of threshold voltage with programming voltage were investigated. The programming voltage was observed in steps of 1V from 10V to 17V and programmed for 1 second. The threshold voltage from 10V to 14V was about 0.5V, which is not much different from that before programing, and the threshold voltages at 15V, 16V and 17V were 1.25V, 2.01V and 3.84V, respectively, which differed 0.75V, 1.49V and 3.44V from that before programing.

• ETRI Journal
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• v.37 no.5
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.1
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• pp.1-5
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• 2008

The output voltage value of AC high voltage source has been usually obtained by multiplying low voltage value measured at both terminals of low voltage resistor by the dividing ratio of the high voltage capacitive divider. From the dividing ratio determined of each 200 kV capacitive divider, we have developed step-up method for measuring the output voltage up to 400 kV using two same type of 200 kV capacitive dividers connected in series. The theoretical dividing ratio of 400 kV capacitive dividers connected in series coincides with that of manufacturer's certification within measurement uncertainty. Thus, this developed step-up method makes it possible to extend the range of output voltage from 200 kV to 400 kV. Furthermore, The dividing ratio of divider under test obtained using this step-up method is consistent with that obtained using one 200 kV high voltage divider within corresponding uncertainties.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.5
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• pp.711-716
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• 2012

To assess the insulation deterioration of stator windings, diagnostic and AC breakdown tests were performed on the eleven high voltage (HV) motors rated at 6kV. After completing the diagnostic tests, the AC overvoltage test was performed by gradually increasing the voltage applied to the stator windings until electrical insulation failure occurred, to obtain the breakdown voltage. Stator winding of motors 1, 3, and 8 failed at above rated voltage at 14 kV, 13.8kV, and 16.4kV, respectively. The breakdown voltage of three motors was higher than expected for good quality windings in 6kV motors. Based on deterioration evaluation criteria, the stator winding insulation of eleven HV motors are confirmed to be in good condition. The turning point of the current, $P_{i2}$, in the AC current vs. voltage characteristics occurred between 5kV and 6kV, and the breakdown voltage was low between 13.8kV and 16.4kV. There was a strong correlation between the breakdown voltage and various electrical characteristics in diagnostic tests including Pi2.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.285-291
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• 2009

In this paper, comparative analysis of offset voltage PWM method and $V_{max}-V_{mid}$ PWM method for three-phase matrix converter is addressed by using a simple analytical and graphical method. Offset voltage PWM method calculates PWM patterns in terms of offset voltage and variable slope of carrier, and it simplifies matrix converter modulation algorithm significantly. $V_{max}-V_{mid}$ PWM method generates patterns by using two phases and maintaining a remaining phase to base phase, and it is implemented in the industrial products. The most important performance criterion of modulation method is a magnitude of current ripples and it is analytically modelled. The graphical illustration of theses complex multivariable functions make per-carrier cycle and per fundamental cycle behavior of two PWM methods understood. Two modulation methods are analysed with the analytical formulas and graphics, and the analysis shows offset voltage PWM method is superior to $V_{max}-V_{mid}$ PWM method with respect to input current ripples and output voltage ripples.