Proceedings of the Korean Institute of Information and Commucation Sciences Conference (한국정보통신학회:학술대회논문집)
- 2013.10a
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- Pages.375-378
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- 2013
Design of Low-Voltage Reference Voltage Generator for NVM IPs
NVM IP용 저전압 기준전압 회로 설계
- Published : 2013.10.25
Abstract
A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's
본 논문에서는 EEPROM이나 MTP 등의 NVM 메모리 IP 설계에 필요로 하는 PVT(Process-Voltage-Temperature) 변동에 둔감한 기준전압(Reference Voltage) 회로를 설계하였다. 매그나칩반도체