• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.793-796
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• 2005

In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

• The Journal of Society for e-Business Studies
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• v.8 no.1
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• pp.1-14
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• 2003

The first edition of ebXML which aims at unimarket was announced at May 1 of 2001. OASIS continues working on the framework of ebXML, and UN/CEFACT does on the contents. In our country, 30 vertical B2B markets are being constructed and most of them adopted ebXML as their main standard. In this situation, we need to make a guideline which can interconnect individual vertical B2B systems. In our study, we propose an architecture for i) Central Registry/Repository for the interconnection of between vertical B2Bs, between ebXML and non-ebXML, and between nations. ii) Information modeling for interconnection. iii) Distributed modeling. We hope our work could be extended by following discussion of academical and industrial researchers.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1467-1474
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• 2010

A tile type active T/R(Transmit/Receive) module for X-band active array radar is demonstrated in this paper. Proposed tile type structure based on fuzz button solderless vertical interconnection shows wide band characteristic of about 30 % bandwidth in X-band with insertion loss of below 0.6 dB and input and output VSWR of less than 1.7. Moreover, the mismatching generally appeared in the vertical interconnection which shown wide band characteristic can also be minimized and, therefore, good gain flatness can be achieved.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.1
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• pp.30-34
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• 2005

This study shows the lasing characteristics of InGaAs/InGaAsP multiple-quantum-well waveguide-type depleted optical thyristor (DOT) using the vertical window. The measured switching voltage and current are 3.36 V and 10 ㎂, respectively. The lasing threshold current is 131 mA at 25 ℃. The output peak wavelength is 1570 nm at a bias current of 1.22 Ith and there is not input signal anymore in the output port. The vertical injection depleted optical thyristor - laser diode (VIDOT-LD) using the vertical-injection structure shows very good isolation between input and output signal.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.720-729
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• 1995

We proposed a XMESH(crossed-mesh) topology as a suitable interconnection for the massively parallel computer architectures, and presented performance analysis of the proposed interconnection topology. Horizontally, the XMESH has the same links as those of the toroidal mesh(TMESH) or toroid, but vertically, it has diagonal cross links instead of the vertical links. It reveals desirable interconnection characteristics for the massively parallel computers as the number of nodes increases, while retaining the same structural advantages of the TMESH such as the symmetric structure, periodic placement of subsystems, and constant degree, which are highly recommended features for VLSI/WSI implementations. Furthermore, n*k XMESH can be easily expanded without increasing the diameter as long as n.leq.k.leq.n+4. Analytical performance evaluations show that the XMESH has a shorter diameter, a shorter mean internode distance, and a higher message completion rate than the TMESH or the diagonal mesh(DMESH). To confirm these results, an optimal self-routing algorithm for the proposed topology is developed and is used to simulate the average delay, the maximum delay, and the throughput in the presence of contention. In all cases, the XMESH is shown to outperform the TMESH and the DMESH regardless of the communication load conditions or the number of nodes of the networks, and can provide an attractive alternative to those networks in implementing massively parallel computers.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.111-114
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• 2002

We propose and fabricate a vertically integrated waveguide thermo-optic switch. It controls the optical path between two vertically stacked waveguide. As a first step, we fabricate polymeric waveguides. The measured propagation loss is ranged from 0.3 db/cm to 0.4 dB/cm at the wavelength of 1.55 $\mu\textrm{m}$. We fabricate the proposed vertically integrated waveguide thermo-optic switch to demonstrate its preliminary feasibility. The measured crosstalk is better than -10 db. The power consumption is about 500 mW. Further effort is necessary to improve its performance.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.