• Journal of the Optical Society of Korea
• /
• v.1 no.1
• /
• pp.44-47
• /
• 1997

The integration of a GaAs/AlGaAs multi-quantum well electroabsorption modulator and a tapered waveguide vertical direction optical interconnect has been performed without the complicated regrowth process. Zn impurity-induced layer disordering of MQW layer is used to achieve the energy transfer between SQW and MQW regions. Light coupled into a SQW region was transferred to an MQW region and an intensity modulation of 10 dB extinction ratio was demonstrated.

• Korean Journal of Materials Research
• /
• v.17 no.7
• /
• pp.347-351
• /
• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the Korea Concrete Institute Conference
• /
• 1992.04a
• /
• pp.95-98
• /
• 1992

In large panel structures, the design of joints which interconnect panels, is important deciding the load-bearing capacity of structures. Being various factors in the design of joints, it is difficult to develop a the critical system for the structural analysis of large concrete panel structures. Therefore there is a tendency to depend on the experiment. The purpose of this paper is to investigate the strength and the mechanical behavior of vertical joints in large concrete panel structures.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.17-24
• /
• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2005.09a
• /
• pp.23-34
• /
• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.112-117
• /
• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• The Journal of Society for e-Business Studies
• /
• v.8 no.1
• /
• pp.1-14
• /
• 2003

The first edition of ebXML which aims at unimarket was announced at May 1 of 2001. OASIS continues working on the framework of ebXML, and UN/CEFACT does on the contents. In our country, 30 vertical B2B markets are being constructed and most of them adopted ebXML as their main standard. In this situation, we need to make a guideline which can interconnect individual vertical B2B systems. In our study, we propose an architecture for i) Central Registry/Repository for the interconnection of between vertical B2Bs, between ebXML and non-ebXML, and between nations. ii) Information modeling for interconnection. iii) Distributed modeling. We hope our work could be extended by following discussion of academical and industrial researchers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.3
• /
• pp.189-192
• /
• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.4
• /
• pp.29-40
• /
• 2004

This paper reports the frequency characteristics and the time response of parallel adjacent-transmission lines, crossed adjacent-transmission lines and parallel adjacent-transmission lines which are on the different planes by using FDTD-PML method. In the parallel adjacent-transmission lines, the crosstalks as a function of horizontal distance are calculated and in the crossed adjacent- transmission lines, the crosstalks as a function of vertical distance are simulated. Also, the crosstalks as functions of horizontal and vertical distances are measured and analyzed in the parallel adjacent-transmission lines which are on the different planes.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.2
• /
• pp.29-36
• /
• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.