• International Journal of Fuzzy Logic and Intelligent Systems
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• 제5권2호
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• pp.102-107
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• 2005

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

• 디지털산업정보학회논문지
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• 제16권1호
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• pp.11-19
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• 2020

IoT has been consistently used in various fields such as smart home, wearables, and healthcare. Since IoT devices are small terminals, relatively simple wireless communication protocols such as IEEE 802.15.4 and ISO 18000 series are used. In this paper, we designed the 802.15.4q 2.4 GHz TASK physical layer. Physical protocol data unit of TASK supports bit-level interleaving and shortened BCH encoding. It is spread by unique ternary sequences. There are four spreading factors to choose the data rate according to the communication channel environment. The TASK physical layer was designed using verilog-HDL and verified through the loop-back test of the transceiver. The designed TASK physical layer was implemented in a fpga and tested using MAXIM RFICs. The PER was about 0% at 10 dB SNR. It is expected to be used in small, low power IoT applications.

• 디지털콘텐츠학회 논문지
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• 제6권3호
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• pp.169-174
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• 2005

본 논문은 Verilog HDL로 FPGA에 JPEG Decoder를 구현하여 TV에 JPEG 영상을 디스플레이 하기 위한 JPEG Image Display Board 설계 방법을 제안한다. 본 논문은 FPGA에 Decoder Algorithm을 구현하기 위한 효율적인 방안을 제시하였으며 JPEG Decoder Algorithm은 JPEG Standard Baseline에 기준으로 하여 설계 하였다. 압축된 JPEG bit stream을 저장하기 위하여 Nand Flash Memory를 사용하였으며, JPEG Decoding된 영상을 TV화면에서 확인하기 위하여 Video Encoder를 사용하였다. 또 한 JPEG 영상에 Text data를 쓰기 위하여 YCbCr의 출력 bit를 RGB 24bit로 변환하였다. Video Encoder에 변환된 RGB Data를 동기시켜 출력하기 위하여 CVBS 입력을 Sync Separator에 의해 Hsync, Vsync, Sync, Field signal로 분리하였다. 또한 Display B/D상의 스위치를 통하여 JPEG 모드와 일반영상 모드를 선택할 수 있게 입증하였다.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.106-111
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• 2020

In this paper, we propose the non-contact gesture recognition system and algorithm using proximity-based sensors. The system uses four IR receiving photodiode embedded on a single chip and an IR LED for small area. The goal of this paper is to use the proposed algorithm to solve the problem associated with bringing the four IR receivers close to each other and to implement a gesture sensor capable of recognizing eight directional gestures from a distance of 10cm and above. The proposed system was implemented on a FPGA board using Verilog HDL with Android host board. As a result of the implementation, a 2-D swipe gesture of fingers and palms of 3cm and 15cm width was recognized, and a recognition rate of more than 97% was achieved under various conditions. The proposed system is a low-power and non-contact HMI system that recognizes a simple but accurate motion. It can be used as an auxiliary interface to use simple functions such as calls, music, and games for portable devices using batteries.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.208-214
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• 2005

A number of watermark insertion method is proposed for the protection of audio contents such as MP3 music. In this paper, we propose a VLSI architecture that performs embedding watermark to the audio signal based on the scheme that proposed by XUEYAO LI[1]. This architecture is implemented and simulated in Verilog HDL. This watermark embedding method used a visually recognizable binary image. Despite a unit that determines the watermark embedded intensity is removed to archive low complexity of H/W, our experimental results show that watermarked signal is perceptually transparency and robust to several known attacks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.285-288
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• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.643-644
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• 2006

In this paper, WiBro system which is one of the mobile wireless metropolitan area network systems is presented. WiBro is an OFDMA system which has a sub-channelization process unlike conventional OFDM systems. The sub-channelization is the time consuming processing, so a time-efficient hardware architecture is needed. WiBro RAS(Radio Access Station) demodulator is designed with Verilog HDL, and the gate count is 81k using the $0.18{\mu}m$ processing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.651-652
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• 2006

In this paper, 4-way data path 128 point pipelined FFT processor with 4-way structure is proposed. The proposed FFT processor has 4-way structure in order to meet data requirement of MB-OFDM system at 132MHz operating frequency. The FFT processor is based on R4MDC and extended to suit 4-way data path. The FFT processor is designed by Verilog HDL and the gate count is about 88k.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.13-14
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show 61.02% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 46.1% cell area reduction.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.527-528
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• 2006

In this paper, we propose an IP design and implementation of System on a chip(SoC) for Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) processor using adder-based DA(Adder-based Distributed Arithmetic). To reduced hardware cost and to improve operating speed, the combined DCT/ DWT processor used the bit-serial method and DA module. The transform of coefficient equation result in reduction in hardware cost and has a regularity in implementation. We use Verilog-HDL and Xilinx ISE for simulation and implement FPGA on SoCMaster-3.