• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.682-684
• /
• 2007

This paper deals the application of sensor network system to fabricate wireless nodes. This node includes a CPLD(XC2C256), FPGA(XC3S1000) a RF module(Bim-433-F), a Hall Sensor and I also develop the CPLD(EPGA) controlling with Verilog-HDL using ISE. The network was consisst of a PC, a Sink node as a gateway, and three Sensor nodes. This sensor network can reaches 40 m with RF interface using by multi-path network.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.7
• /
• pp.1653-1659
• /
• 2013

In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.05a
• /
• pp.656-658
• /
• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Journal of IKEEE
• /
• v.27 no.4
• /
• pp.573-578
• /
• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.04a
• /
• pp.43-45
• /
• 2001

본 논문에서는 MPEG 비디오 코어 프로파일 디코더 ASIC 상위 구조 설계를 시스템 수준에서 검증하는 기법을 제시한다. 상위 구조 설계는 RISC 프로세서와 펌웨어 그리고 일반 로직이 병존하는 혼합형 구조라는 것과 설계의 상위 단계라는 특징을 가지고 있기 때문에 Verilog HDL과 CSIM 모델 두 가지 모델이 혼합되어 있다. 통합 환경은 C 언어를 이용한 하드웨어 모델링 기법과 PLI를 통한 프로그래밍 언어와 Verilog의 통합 방법을 이용하여 설계 단계에서 각 블록의 특성에 가장 적합한 모델을 이용하여 동작 검증이 가능하도록 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.05a
• /
• pp.768-770
• /
• 2014

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of multiplication server farms. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• The Journal of the Convergence on Culture Technology
• /
• v.9 no.6
• /
• pp.967-971
• /
• 2023

Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.9C
• /
• pp.871-876
• /
• 2005

In this paper, we propose an improved partial response maximum likelihood (PRML) detection scheme that has an adaptive equalizer and can be applied in the asymmetric optical recording system with high-density. We confirmed that the proposed PRML detector improves detection performance. In addition, we implemented the detector by Verilog HDL. The adaptive equalizer is composed of tap coefficient updating unit using LMS algorithn and FIR filter. FIR filter is implemented by the transposed direct form architecture for high speed operation. Viterbi detector is implemented by the register exchange method.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.67 no.1
• /
• pp.9-14
• /
• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.10a
• /
• pp.1027-1030
• /
• 2015

하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.