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http://dx.doi.org/10.6109/jkiice.2013.17.7.1653

Automatic Visual Architecture Generation System for Efficient HDL Debugging  

Moon, Dai-Tchul (Department of Information & Communication Eng., Hoseo University)
Cheng, Xie (Department of Information & Communication Eng., Hoseo University)
Park, In-Hag (Department of Information & Communication Eng., Hoseo University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.17, no.7, 2013 , pp. 1653-1659 More about this Journal
Abstract
In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.
Keywords
Verilog/VHDL SPD; Archian; debugging; placement/routing; message passing;
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  • Reference
1 Hyung-Lae Roh, "Driving forces & the technological challenges for SOC development of tomorrow", Signal Processing Systems, Aug. 2003.
2 Yuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su, "An embedded in-circuit emulator generator for SOC platform", Field-Programmable Technology (FPT), Dec. 2003.
3 Wooseung Yang, Moo-Kyeong Chung, "Current Status and Challenges of SoC Verification for Embedded Systems Market", IEEE International SOC Conference, pp.213-216, Sept. 2003.
4 Min Pan, Chu C, "IPR: An Integrated Placement and Routing Algorithm," Design Automation Conference, pp. 59-62, 2007.
5 Chih-Wen Hsueh, Tien-Fu Chen, "Development of architecture and software technologies in high-performance low-power SoC design", Embedded and Real-Time Computing Systems and Applications, pp.475-480, Aug. 2005.
6 Ruan, A.W, Li, C.Q, Song, Z.J., Chen, J., Deng, L.X., Hou, H.C. Liao, Y.B., "The third generation verification technology based SOC debugging", Computational Problem-Solving (ICCP), pp. 109-114, Oct. 2011.
7 Park, S.-Y., Lee, J. and Hariri,S., "A multithreaded message-passing system for high performance distributed computing applications," in Distributed Computing Systems, pp. 258-265, 1998.
8 Choe, Y.K., Agrawal, D.P., Green, C.R. "A hierarchical message mechanism for distributed systems software", Distributed Computing Systems in the 1990s, 1988.
9 Jung, M., Biersack, E.W., "A component-based architecture for software communication systems", Engineering of Computer Based Systems, 2000.
10 Jie Liang, Mao Lin Huang, "Highlighting in Information Visualization A Survey", Information Visualisation (IV), July 2010.
11 Sherman, Alan T.(Alan Theodore). Springer-Verlag, "VLSI placement and routing: the PI project", Springer, 1989.
12 Koschella, James J., "A placement/interconnect channel router: cutting your PI into slices", B.S. thesis, Department of Computer Science, MIT, 1981.
13 Sechen, Carl, "VLSI placement and global routing using simulated annealing", Kluwer Academic Publishers, 1988.