• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.781-784
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• 1993

Most linguistic models of processes or plants known are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show two models for synchronous finite state machines (FSM) based on fuzzy logic, namely the Crisp-State-Fuzzy-Output (CSFO FSM) and Fuzzy-State-Fuzzy Output (FSFO FSM). As a result of the introduction of the FSM models, the improved architectures for fuzzy logic controller have been defined. These architectures featuring pipelined intelligent fuzzy controller are discussed in terms of dimensionality of the model. VLSI integrated circuit implementation issues of the fuzzy logic controller are also considered. The presented approach can be utilized for fuzzy controller hardware accelerators intended to work in the real-time environment.

• 대한전자공학회논문지
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• 제23권3호
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• 전자공학회논문지C
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• 제35C권12호
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• pp.13-22
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• 1998

본 논문에서는 CMOS VLSI 회로의 IDDQ 테스팅을 위한 0.8㎛ single-poly two-metal CMOS 공정으로 제작된 고성능 내장형 전류감지기를 제안한다. 테스트 대상회로는 브리징 고장이 존재하는 4 비트 전가산기를 사용하였다. 크기가 다른 두 개의 nMOS를 사용하여 저항값이 다른 두 개의 브리징 고장을 삽입하였다. 그리고 게이트 단자를 제어하여 다양한 고장효과를 실험하였다. 제안된 내장형 전류감지기는 테스트 대상회로에 사용되는 클럭의 주기 끝에서 고장전류를 검사하여 기존에 설계된 내장형 전류감지기 보다 긴 임계전파지연 시간과 큰 면적을 가지는 테스트 대상회로를 테스트 할 수 있다. HSPICE 모의실험과 같이 제작 칩의 실험결과 제안한 내장형 전류감지기가 회로 내에 삽입된 브리징 고장을 정확하게 검출함을 확인하였다.

• 대한전자공학회논문지TE
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• 제37권5호
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• pp.7-16
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• 2000

본 논문은 고속 지수 선택기를 이용한 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 구현에 관하여 기술하였다. 본 제산/스퀘어-루트는 처리 속도 25㎒를 갖는 여분 이진수의 가산 방식을 사용하여 올림수 지연을 제거함으로써 비트 크기에 관계없이 일정한 시간으로 가산을 수행한다. 각각의 반복 단계에 널리 사용된 제산과 스퀘어-루트에 대해 16-비트 VLSI 회로를 설계하였다. 이것은 매번 16개 클럭마다 시프트된 이진수를 여분 가산하여 제산 및 스퀘어-루트를 실행한다. 또한 이 회로는 비복원 방법을 사용하여 지수 비트를 얻는다. 지수 선택 논리의 간단한 회로를 구현하기 위하여 나머지 비트의 주요 세 자리를 사용하였다. 결과적으로, 이 회로의 성능은 새로운 지수 선택 가산 논리를 적용하여 지수 결정 영역을 병렬 처리함으로써 한층 더 연산 처리 속도를 높인 것이다. 이전에 동일한 알고리즘을 사용하여 제안된 설계보다 13% 빠른 속도 증가를 보였다.

• 한국컴퓨터정보학회논문지
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• 제17권3호
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• pp.1-10
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• 2012

본 논문에서는 계수순환과 기약 삼항식을 적용하여 시스템 복잡도를 개선한 GF($2^m$)상의 승산기 구성방법과 구현회로를 제안하였다. 제안된 회로는 병렬 입출력 구조를 가지며, 승산항의 계수 순환과 기약 삼항식을 적용한 모듈로 연산을 하는 회로 구성의 특성상 기존의 타 논문에 비해 회로 복잡도가 감소함을 보였다. 본 논문에서 제안한 회로의 시스템 복잡도는 $2m^2$개의 2-입력 AND 게이트, m (m+2)개의 2-입력 XOR 게이트의 회로복잡도이며, 메모리나 스위치 등의 별도의 소자는 필요하지 않다. 연산에 소요되는 최대 지연시간은 $T_A+(2+{\lceil}log_2m{\rceil})T_X$ 이다. 본 논문에서 제안한 회로는 간단하고, 정규성을 보이며, 모듈구성이 가능하기 때문에 VLSI 회로구성에 상대적으로 적합하다.

• 대한전자공학회논문지
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• 제25권5호
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• 전자공학회논문지C
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• 제34C권10호
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• pp.59-66
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• 1997

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

• ETRI Journal
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• 제31권2호
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2007년도 추계학술발표논문집
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• pp.78-80
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• 2007

According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.