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http://dx.doi.org/10.9708/jksci.2012.17.3.001

A Study on the Construction of Parallel Multiplier over GF2m)  

Han, Sung-Il (Dept. of Information & Telecommunication, Induk College)
Publication Information
Journal of the Korea Society of Computer and Information / v.17, no.3, 2012 , pp. 1-10 More about this Journal
Abstract
A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.
Keywords
Finite field; Irreducible trinomial; multiplier; Finite field multiplication;
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