• ETRI Journal
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• v.27 no.6
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• pp.691-696
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• 2005

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a $5{\times}5$ matrix of data cells in a Virtex-E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1205-1214
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• 2004

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.138-144
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• 1989

In this paper, a new method is proposed to remove the logical redundancy for the gate-level circuit optimization. In this method, only the fanout-branch signals in the circuits, not all the signals, are examined for redundancy. When a signal is determined to be nonredundant, other nonredundant signals are found out by the efficient procedure, using only the informations which are generated in the course of the redundancy-check. In order to avoid the re-examination of a signal for redudancy, a heuristic method is proposed to determine the redundancy-checking order of signals. The proposed method is heuristic, based on the VLSI test theory. It is much faster than other methods, since it does not reexamine a signal for redundancy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2303-2307
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• 2006

The round off noise properties of wave digital filters have known and desirable properties in respect to their realization with short coefficient wordlengths. This paper presents the optimal implementation of wave digital filters by employing multiprocessor archtectures in the sense of input sampling rate, the number of processors, and input-output delay. The implementation will be specified by complete circuit diagrams including control signals, and can be applied to an existing silicon complier for VLSI layout generation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.281-284
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• 1998

In this paper, a RS(Reed-Solomon) docoder is designed in the transform domain instead of most time domain. The transform RS decoder have simpler structure for error-correction procedure but because of his larger chip area, the time domain RS decoder is popular currently. To solve this proplem, the nomal basis representation and the conjugate property is utilized. Therefore the chip area can be reduced for the stucture of syndrome delay, nomalization and inverse transform circuit. These modified structures have been implemented using VHDL and synthesized on 0.8${\mu}{\textrm}{m}$ CMOS technology. The results have been compared with other structure for chip area and performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.3
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• pp.329-333
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• 1998

본 논문에서는, LSI 적층 기술을 이용한 실시간 처리 마이크로 비젼의 개발을 소개하고 있다. 새롭게 개발된 LSI 적층기술을 이용하여, 영상신호의 증폭, 변환, 연산처리등의 기본기능을 가지는 다수의 LSI 웨이퍼를 적층한다. 각 층간의 고밀도 수직배선을 통하여 대량의 영상정보를 동시에 전달하므로써, 대규모 동시 병렬처리를 가능하게 하며, 다수의 층에 걸쳐 파이프 라인 처리가 이루어진다. VLSI 설계시스템을 이용하여, 윤곽 검출기능을 가지는 테스트 칩을 설계(2 .mu.m CMOS design rule)하고, 시뮬레이션을 통하여 양호한 동작(처리시간 10 .mu.s)을 확인하고 있다. 시험제작을 위해서는, 새롭게 개발된 LSI 적층기술이 이용된다. 영상처리의 기본회로가 실려있는 웨이퍼의 기반을 30 .mu.m 의 두께까지 연마하고, 개발된 웨이퍼 aligner를 이용하여 수직배선이 형성된 상하 두 개의 웨이퍼를 미세조정하면서 접착한다. 이상의 제작과정을 반복하여 두께 1mm이하의 인공망막과 같은 마이크로 비젼을 제작한다.