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An Efficient Collapsing Algorithm for Current-based Testing Models in CMOS VLSI  

Kim Dae lk (여수대학교 자연과학대학 반도체학과)
Bae Sung Hwan (한려대학교 멀티미디어정보통신공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.29, no.10A, 2004 , pp. 1205-1214 More about this Journal
Abstract
For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.
Keywords
Testing; Fauit collapsing; CMOS VLSI;
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1 T. Shinogi and T. Hayashi, 'An iterative improvement method for generating compact tests for IDDQ testing of bridging faults,' IEICE Trans. INF & SYST., Vol. E81-D. No. 7, July 1998
2 R. C. Aitken, 'A Comparison of Defect Models for Fault Location with Iddq Measurements,' Proc. ITC'92, pp. 778-787, Sept. 1992
3 X. Wen, H. Tamamoto and K. Kinoshita, 'IDDQ Test Vector Selection for Transistor Short Fault Testing,' System and Computers in Japan, vol. 28, no. 5, 1997
4 P. J. Thadikaran, 'Evaluation, selection and generation of IDDQ tests,' PHD. Thesis, Department of Computer Science, State University of New York, 1996
5 R. Rajsuman, IDDQ Testing for CMOS VLSI, Artech House, 1994
6 홍성제 외, 테스팅 및 테스팅을 고려한 설계, 홍릉과학출판사, 2000
7 S. Chakravarty and S. T. Zachariah, 'STBM: A Fast Algorithm to Simulate IDDQ Tests for Leakage Faults,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 568-576, May 2000   DOI   ScienceOn
8 Rochit Rajsuman, 'Iddq Testing CMOS VLSI,' Proceedings of The IEEE, vol. 88, no. 4, pp. 544-566, April 2000   DOI   ScienceOn
9 W. Mao and R. K. Gulati, 'QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults,' Proc. ICCAD'90, pp. 280-283, 1990
10 T. Lee, I. N. Hajj, E. M. Rudnick, J. H. Patel, 'Genetic-algorithm based test generation for current testing of bridging faults in CMOS VLSI circuits,' IEEE VLSI Test Symposium, pp. 456-462, 1996