• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.1
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• pp.23-31
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• 2005

Recently, the multimedia and high speed telecommunication systems needs a high frequency and high stability oscillator. The VCXO(voltage controlled -crystal oscillator) have continually downsized to gratify a thin and small size of the telecommunication systems. In his paper, we have developed the small ceramic PECL(positive emitter-coupled logic) VCXO of the 5×7 mm size for gratifying the requested specifications from user, and then use the multilayer ceramic SMD(surface mounted device) package technology. The ceramic SMD PECL VCXO is operating at the 3.3 Voltage and have the frequency range of 120MHz～180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.45-52
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• 2006

In his paper, we have developed the SMD(surface mounted device) type PECL(positive emitter-coupled logic) VCXO of the $5{\times}7mm$ size for gratifying the requested specifications and the multilayer ceramic SMD(surface mounted device) package technology. The VCXO wired with the PECL(positive emitter coupled logic) package take place a stray inductance and a parasitic capacitance by the length and the inner pattern of the VCXO and the amplitude attenuation and signal loss due to the reflection of power source and the noise component. We have developed the Zig system to analyze the precise spectrum and evaluate the performance. The basic operating voltage is the 3.3 V and have the frequency range of 120MHz-180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.107-113
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• 2005

In this paper, we have developed the miniature ceramic PECL(positive emitter-coupled logic) VCXO of the $5{\times}7mm$ size for gratifying the requested specifications and the multilayer ceramic SMD(surface mounted device) package technology. The ceramic SMD PECL VCXO designed by the inverted Mesa type HFF is operating at the 3.3 Voltage and have the frequency range of 120MHz-180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.61-64
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• 2005

본 연구에서는 $5mm{\times}7mm$ 크기의 적층 세라믹 SMD(surface mounted device)형 PECL VCXO에 테스트지그를 이용하여 스펙트럼을 분석한다. 패키지에 PECL 칩을 장착 후 와이어결선(wire bonding)을 완료한 VCXO는 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스(stray inductance) 및 커패시턴스가 발생하고, 칩의 발진부 임피던스에 영향을 준다. 이에 칩이 패키지에 장착된 상태에서 발진부 입력임피던스 영향을 제거하고 안정한 발진기 측정을 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가한다.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1885-1890
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• 2003

In this paper, we have developed the voltage controlled crystal oscillator (VCXO) with positive emitter coupled logic(PECL). The VCXO is a crystal oscillator which includes a varactor diode and associated circuitry allowing the frequency to be changed by application of a voltage across that diode. The characteristics of the PECL has the delay time less than 2 ns and the faster logic gate, and the high level output greater than 2.3 V and the low level output smaller than 1.68 V.

• Journal of Korean Electronics
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• v.24 no.7
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• pp.58-59
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• 2004

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.739-745
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• 1993

In mobile communication instruments, realization of the frequency synthesizer with high stabililty in temperature is very important. In order to realize a high stability frequency synthesizer, the oscillator providing for reference frequency must be stabilized in various temperature. In accordance to this requirement, the TCXO using digital method is rrealized in this thesis. The DTCXO consists of temperature sensing part, control part and the VCXO. The frequency stability of the realized DTCXO is 0.94 ppm on average. This is an improved result when compared with the 2.5 ppm of the TCXO using analog method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.93-97
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• 2007

In this paper a new clock generation scheme for TDM-CDM converter in the Gap Filler for satellite DMB systems has been proposed. The scheme uses the frame sync signal from the Ku band TDM receiver to lock the VCXO which provides the system clock for the TDM-CDM converter. The locking algorithm can be easily implemented in the FPGA, so that no separate circuitry is needed as in conventional PLL. With a stable OCXO, The scheme can be used to generate the reference clock to the local oscillator for RF parts.

• Journal of Power System Engineering
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• v.14 no.1
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• pp.5-10
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• 2010

Both the accuracy and stability of the clock get from the GPS receiver are considered in the range of pps. And we verified the system clock stability of a micro-controller system using the pps pulse supplied by the GPS receiver. In complex system of digital processing, the rack of precise timing signal may cause the serious problem or breakdown accident. To get rid of these undesirable problems, we introduced VCXO circuit to a micro-controller system to preserve high accurate clock stability.