• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.12-13
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• 2010

본 논문에서는 USB(Universal Serial Bus) 인터페이스를 이용하여 PC와 하드웨어 사이의 영상을 송수신 하는 시스템을 제안한다. 구현된 시스템은 PC에서 스테레오 캠으로부터 획득된 좌안, 우안 영상을 USB 인터페이스를 이용하여 고속으로 하드웨어에 전송해주고, 하드웨어에서 생성된 깊이 맵을 고속으로 전송받도록 구성되어 있다. Cypress사의 USB2.0 컨트롤러 칩인 CY68013A를 사용하여 구현하였으며, USB칩과 FPGA와의 인터페이스는 GPIF(General Programmable Interface)를 이용하여 병목현상이 없이, 고속의 데이터 전송을 달성하도록 하였다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1638-1639
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• 2011

본 논문에서는 초소형 무선 USB 동글 장치를 위한 광대역 접힌(folded) 모노폴 안테나를 제안하였다. 제안된 안테나는 CPW 급전으로부터 삼지창 형상의 선로를 적용하여 광대역 특성을 구현하였다. 최종 설계된 안테나의 크기는 $16{\times}44.8{\times}3.5\;mm^3$이며, low-profile의 무선 USB 동글용 안테나에 적합하다. 제안된 안테나는 $S_{11}$ < -10 dB 기준으로 2.28~10.8 GHz의 공진 주파수 대역을 가지므로 WiBro (2.3~2.4 GHz), Bluetooth (2.4~2.484 GHz), WiMAX (2.5~2.7 GHz, 3.4~3.6 GHz), satellite DMB (2.605~2.655 GHz), 802.11b/g/a WLAN (2.4~2.485 GHz, 5.15~5.825 GHz), UWB(3.1~10.6 GHz)의 무선 대역을 지원 할 수 있다. 측정된 평균 이득의 범위는 -3.41 dBi 에서 -0.84 dBi 이다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10b
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• pp.412-414
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• 2001

In this paper, we describe an real-time facial feature tracker. We only used a general USB PC Camera without a frame grabber. The system has achieved a rate of 8+ frames/second without any low-level library support. It tracks pupils, nostrils and corners of the lip. The signal from USB Camera is YUV 4:2:0 vertical Format. we converted the signal into RGB color model to display the image and We interpolated V channel of the signal to be used for extracting a facial region. and we analysis 2D blob features in the Y channel, the luminance of the image with geometric restriction to locate each facial feature within the detected facial region. Our method is so simple and intuitive that we can make the system work in real-time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.7-11
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• 2013

Wearable computer systems use the wireless universal serial bus (WUSB), which refers to USB technology that is merged with WiMedia physical layer and medium access control layer (PHY/MAC) technical specifications. WUSB can be applied to wireless personal area network (WPAN) applications as well as wired USB applications such as PAN. WUSB specifications have defined high-speed connections between a WUSB host and WUSB devices for compatibility with USB 2.0 specifications. In this paper, we focus on an integrated system with a WUSB over an IEEE 802.15.6 wireless body area network (WBAN) for wireless wearable computer systems. Due to the portable and wearable nature of wearable computer systems, the WUSB over IEEE 802.15.6 hierarchical medium access control (MAC) protocol has to support power saving operations and integrate WUSB transactions with WBAN traffic efficiently. In this paper, we propose a low-power hibernation technique (LHT) for WUSB over IEEE 802.15.6 hierarchical MAC to improve its energy efficiency. Simulation results show that the LHT also integrates WUSB transactions and WBAN traffic efficiently while it achieves high energy efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2223-2231
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• 2015

In this paper, we propose a built-in antenna for wireless USB dongle which has a modified structure from the existing planar monopole antenna. The proposed antenna implemented a dual-band characteristic by inserting Strip1, Strip2, Strip3 into the monopole structure combined with 'n' shape and feeded 50-Ω using coaxial cable. The antenna is designed on an FR-4 substrate of which the dielectric constant is 4.6, and its overall size is 10 mm × 50 mm × 1mm. Based on the measurement results of the return loss, it was confirmed to satisfy the dual band resonance characteristics of 740 MHz (2.3 ~ 2.7 GHz) and 1,200 MHz (5.15 ~ 5.825 GHz) by -10 dB. In addition, we obtain the omni-directional radiation pattern measurements in the operating frequency bands, and the maximum gain of the proposed antenna has 2.26~3.81 dBi in the 2.4 GHz band and 2.21~5.79 dBi. in the 5.5 GHz band, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.155-167
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• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• Journal of Internet Computing and Services
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• v.12 no.5
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• pp.21-28
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• 2011

Recently medical and entertainment applications using conducting textile are suggested, but the data of conducting threads are not characterized, classified and verified. Only the data sheet published by manufacturing companies is available. Thus we need to verify the performances of the threading threads in communication. And we need a guideline if the existing communication protocols can be used for the conducting threads communication or the new specific communication protocols have to be developed for the communication. This paper classifies the characteristics of conducting threads made by domestic and overseas companies. Based on the criteria we classified conducting threads into three classes: class A, class B and class C. Further we carried out experiments to verify the adaptability of existing simple serial communication protocols such as RS232. Six different conducting threads are used in experiments and the length of each thread was 0.5m, 1m, 2m and 3m. The data transmission rate and error rate are collected and analyzed. RS485 is very prone to error due to static electricity from human and environment. So it may not be appropriate as long-distance communication protocol up to 12km which is possible in theory. RS232 shows stable and error-less data transmission ability even though every conducting thread didn’t show transmission capability over RS232. USB protocol shows high data rate transmission but the distance cannot be exceeded over 2m. Additionally, USB requires stable power supply. But if the power is supplied through conducting thread, its function is not.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.135-140
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• 2014

In this paper, we describe the contents of noise characteristic enhancement using digital filtering to the motion vector in the pattern noise of optical mouse. The designed circuit is implemented to enhance the smoothing and trembling with filtering and averaging of x, y motion vector before PS2 or USB output. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 6MHz and the motion vector has the range of +6 to -6 per 1/1700sec. It is tested using the Cartesian robot to measure the noise characteristic enhancement.