JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0

  • Seong, Kihwan (Department of Electronic and Electrical Engineering from POSTECH) ;
  • Lee, Won-Cheol (Department of Electronic and Electrical Engineering from POSTECH) ;
  • Kim, Byungsub (Department of Electronic and Electrical Engineering from POSTECH) ;
  • Sim, Jae-Yoon (Department of Electronic and Electrical Engineering from POSTECH) ;
  • Park, Hong-June (Department of Electronic and Electrical Engineering from POSTECH)
  • Received : 2015.11.30
  • Accepted : 2016.02.11
  • Published : 2016.06.30
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Abstract

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

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References

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