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http://dx.doi.org/10.5573/JSTS.2016.16.3.352

All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0  

Seong, Kihwan (Department of Electronic and Electrical Engineering from POSTECH)
Lee, Won-Cheol (Department of Electronic and Electrical Engineering from POSTECH)
Kim, Byungsub (Department of Electronic and Electrical Engineering from POSTECH)
Sim, Jae-Yoon (Department of Electronic and Electrical Engineering from POSTECH)
Park, Hong-June (Department of Electronic and Electrical Engineering from POSTECH)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.16, no.3, 2016 , pp. 352-358 More about this Journal
Abstract
A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.
Keywords
Multi-phase; ring oscillator; digitally controlled oscillator (DCO); phase-locked loop;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa, "A $0.032mm^2$ $780{\mu}W$ Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase Coupled Oscillator Using Edge-Injection Technique," IEEE ISSCC Dig. Tech. Paper, pp. 266-267, 2014.
2 Muhammad Faisal and David D. Wentzloff, "An Automatically Placed-and-Routed ADPLL for the MedRadio Band using PWM to Enhance DCO Resolution," IEEE RFIC, pp. 115-118, 2013.
3 Werner Grollitsch, Roberto Nonis and Nicola Da Dalt, "A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS," IEEE ISSCC Dig. Tech. Paper, pp. 478-479, 2010.
4 Robert Bogdan Staszewski, Porast Balsara, "All-digital frequency synthesizer in deep-submicron cmos"
5 Pyoungwon Park, Jaejin Park, Hojin Park, Seonghwan Cho, "An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS," IEEE ISSCC Dig. Tech. Paper, pp. 336-337, 2012.
6 Yongsam Moon, "A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique," J. Semicond. Technol. Sci., vol. 14, no. 3, pp. 331-338, June. 2014.   DOI
7 Chao-Ching Hung and Shen-Iuan Liu, "A leakage-suppression technique for phase locked systems in 65nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 400-401, 2009.
8 Yuanfeng Sun, Jun Li, Zhuo Zhang, Min Wang, Ni Xu, Hang Lv, Woogeun Rhee, Yongming Li, Zhihua Wang, "A 2.74-5.37GHz Boosted-Gain Type-I PLL with <15% Loop Filter Area," IEEE RFIC, pp. 181-184, 2012.
9 Wooseok Kim, Jaejin Park, Jihyun Kim, Taeik Kim, HoJin Park, and DeogKyoon Jeong, "A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range," IEEE ISSCC Dig. Tech. Paper, pp. 250-252, 2013.