• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.565-568
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• 1998

The effects of denudation anneals on the properties of 256Mega-bit level devices were investigated. Based on the three-step anneal model, the redistribution of oxygen atom and the defect free zone depth were calculated. A significant outdiffusion of oxygen atoms is occurred during the denudation anneals at high temperature. Junction leakage current of P+/N-Well and N+/P-Well junctions, as a function of denudation anneal temperature, was decreased with increase of anneal temperature and is closely related with the behaviors of oxygen atoms. Also it is found that the denudation anneal at high temperature very effective for the fabrication of reliable 256Mega-bit level devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.86-86
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• 2003

Copper has attracted much attention in the deep submicron ULSI metallization process as a replacement for aluminum due to its lower resistivity and higher electromigration resistance. Electroless copper deposition method is appealing because it yields conformal, high quality copper at relatively low cost and a low processing temperature. In this work, it was investigated that effect of the microstructure of the substrate on the electroless deposition. The mechanism of the nucleation and growth of the palladium nuclei during palladium activation was proposed. Electroless copper deposition on TiN barriers using glyoxylic acid as a reducing agent was also investigated to replace toxic formaldehyde. Furthermore, electroless copper deposition on TaN$\sub$x/ barriers was examined at various nitrogen flow rate during TaN$\sub$x/ deposition. Finally, it was investigated that the effect of plasma treatment of as-deposited TaN$\sub$x/ harriers on the electroless copper deposition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.6
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• pp.459-466
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• 2000

For the applications in the ultra-large-scale-integration (ULSI) metallization processing copper thin films have been prepared by metal organic chemical vapor deposition (MOCVD) technology on TiN/Si substrates. The films have been deposited with varying the experimental conditions of substrate temperatures and copper source vapor pressures. The films were then annealed in a vacuum condition after the deposition and the annealing effect to the electrical conductivity of the films was measured. The grain size and the crystallinity of the films were observed to be increased by the post annealing and the electrical conductivity was also increased. The best electrical property of the copper film was obtained by in-situ annealing treatment at above 40$0^{\circ}C$ for the sample prepared at 18$0^{\circ}C$ of the substrate temperature.

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.23-27
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• 2008

The effect of solution agitation on the copper electroless deposition process of ULSI (ultra large scale integration) interconnections was investigated by using physical, electrochemical and electrical techniques. It was found that proper solution agitation was effective to obtain superconformal copper configuration within the trenches of $130{\sim}80nm$ width. The transition of open potential during electroless deposition process showed that solution agitation induced compact structure of copper deposits by suppressing mass transfer of cuprous ions toward substrate. Also, the specific resistivity of copper layers was lowered by increasing agitation speed, which made the deposited copper particles smaller. Considering both copper deposit configuration and electric property, around 500 rpm of solution agitation was the most suitable for the homogeneous electroless copper filling within the ultra-fine patterns.

• Electrical & Electronic Materials
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• v.6 no.3
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• pp.269-275
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• 1993

미래의 ULSI 소자의 게이트 산화막으로 이용하기 위하여 $N_{2}$O 가스 분위기에서 기존의 전기로를 이용한 실리콘의 열산화에 의해 $N_{2}$O 산화막을 형성하였고 MOS 소자를 제작하여 전기적 특성을 고찰하였다. 900.deg.C에서 90분간 산화한 $N_{2}$O 산화막의 경우, 플랫밴드 전압( $V_{FB}$ ), 고정전하밀도 ( $N_{f}$)와 플랫밴드 전압의 변화량(.DELTA. $V_{FB}$ )은 각각 0.81[V], 6.7x$10^{10}$[$cm^{-2}$]와 80~95[mV]를 나타내었다. $N_{2}$O 산화막의 전기전도기구는 저전계 영역에서는 Fowler-Nordheim 터널링, 고전계영역에서는 Poole-Frenkel 방출이 지배적으로 나타났고 절연파괴전계는 16[MV/cm]로 높게 나타났다. 따라서 $N_{2}$O 산화로 형성된 게이트 산화막이 ULSI소자의 게이트 유전체로 응용이 가능하리라 생각된다..

• Ceramist
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• v.4 no.1
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• pp.5-13
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• 2001

차세대 ULSI 소자의 다층금속배선을 위한 저유전 물질중에서, 기존의 절연막인 TEOS-$SiO_2$ 증착 장비 및 공정을 최대한 이용할 수 있으며, 물성 또한 TEOS oxide와 유사하다는 점에서 적용 시점을 앞당길 수 있는 SiOF 박막과 SiOC 박막의 특성에 대해 고찰해 보았다. 1세대 저유전 물질이라 할 수 있는 SiOF는 후속공정에도 안정적인 상태의 박막을 얻기 위해서는 3.0이하의 유전상수를 얻는 것이 불가능한 반면, SiOC는 3.0 이하의 유전상수를 가지는 안정적인 박막을 얻을 수 있다. SiOC 물질은 저밀도의 단일물질로서, 물질 내부에 후속공정에 영향을 미칠만한 기공을 포함하지 않기 때문에 후속 CMP 공정에 적합하였으며, $450^{\circ}C$이하의 열 공정에서도 응력변화 및 박막성분 탈착이 거의 일어나지 않는 점 또한 SiOC 박막의 우수한 후속공정 적합성을 보여주는 결과였다. 이러한 결과를 종합하여 볼 때, 현재 사용되고 있는 1세대 저유전 물질인 SiOF 박막을 대체할 차세대 저유전 물질로 SiOC 물질이 유망하며, 이는 3.0 이하의 유전상수를 요구하는 Gb DRAM 소자나 보다 빠른 동작속도가 생명인 논리회로(logic circuit) 소자에 적용될 경우 큰 소자특성 개선이 기대된다.

• Proceedings of the Korean Ceranic Society Conference
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• 2003.04a
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• pp.17.1-17
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• 2003

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.31-31
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• 2004

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.11a
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• pp.91-92
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• 1993

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.11a
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• pp.18-18
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• 1993