• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.3
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• pp.231-244
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• 2013

We introduce the concept of interval-valued fuzzy congruences on a semigroup S and we obtain some important results: First, for any interval-valued fuzzy congruence $R_e$ on a group G, the interval-valued congruence class Re is an interval-valued fuzzy normal subgroup of G. Second, for any interval-valued fuzzy congruence R on a groupoid S, we show that a binary operation * an S=R is well-defined and also we obtain some results related to additional conditions for S. Also we improve that for any two interval-valued fuzzy congruences R and Q on a semigroup S such that $R{\subset}Q$, there exists a unique semigroup homomorphism g : S/R${\rightarrow}$S/G.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.12 no.3
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• pp.205-214
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• 2012

We study some properties of interval-valued fuzzy normal subgroups of a group. In particular, we obtain two characterizations of interval-valued fuzzy normal subgroups. Moreover, we introduce the concept of an interval-valued fuzzy coset and obtain several results which are analogous of some basic theorems of group theory.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.1
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• pp.66-70
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• 2007

Note that Choquet integral is a generalized concept of Lebesgue integral, because two definitions of Choquet integral and Lebesgue integral are equal if a fuzzy measure is a classical measure. In this paper, we consider interval-valued Choquet integrals with respect to fuzzy measures(see [4,5,6,7]). Using these Choquet integrals, we define a mappings on the classes of Choquet integrable functions and give an example of a mapping defined by interval-valued Choquet integrals. And we will investigate some relations between m-convex mappings ${\phi}$ on the class of Choquet integrable functions and m-convex mappings $T_{\phi}$, defined by the class of closed set-valued Choquet integrals with respect to fuzzy measures.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.675-676
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• 2013

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing and common multi-terminal extension decision diagrams. The common multi-terminal extension decision diagrams represents extension valued multiple-output functions, while time domain based on multiplexing systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams, that is the common binary decision diagrams and common multi-terminal extension decision diagrams.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1774-1779
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• 2005

This paper propose the design method of the constructing the digital logic systems over galois fields using by the galois field decision diagram(GFDD) that is based on the graph theory. The proposed design method is as following. First of all, we discuss the mathematical properties of the galois fields and the basic properties of the graph theory. After we discuss the operational domain and the functional domain, we obtain the transformation matrixes, $\psi$GF(P)(1) and $\xi$GF(P)(1), in the case of one variable, that easily manipulate the relationship between two domains. And we extend above transformation matrixes to n-variable case, we obtain $\psi$GF(P)(1) and $\xi$GF(P)(1). We discuss the Reed-Muller expansion in order to obtain the digital switching functions of the P-valued single variable. And for the purpose of the extend above Reed-Muller expansion to more two variables, we describe the Kronecker product arithmetic operation.