• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.179-181
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• 2009

고압 방전 램프는 점등 후부터 정상상태에 이르기까지 방전관 내부의 온도 및 압력이 광범위하게 변화하는 복잡한 동작 특성으로 모델링이 어렵다. 이러한 특성은 램프를 구동하는 안정기의 설계에 어려움이 따른다. 램프의 구동에는 초기 점화 시 높은 점화용 전압 펄스를 필요로 한다. 점화 후에 정상상태에 다다르면 램프 전극의 소모를 줄이기 위해 교류로 구동되어야 한다. 하지만 램프를 교류로 구동하게 되면 음향 공진 현상이 발생할 수 있다. 음향 공진 현상은 램프 구동 전류의 맥동성분이 큰 경우에도 발생을 할 수 있으므로 구동 전류의 맥동 성분의 크기는 최소화 돼야 한다. 램프의 수명시간을 길게 하려면, 안정기는 램프를 정격전력으로 구동하여야 한다. 따라서 안정기에서는 정전력 제어가 필요하게 된다. 램프 전류의 극성이 변화할 때, 램프 전류는 spike전류와 중첩이 된다. 본 논문에서는 spike 전류를 저주파구형파 램프 전류의 포락범위 안에 유지하고, 고주파 스위칭시손실을 줄이기 위해 소프트 스위칭 기법을 이용한 회로 설계를 제안했다. 제안된 방법은 시뮬레이션 및 이론적 수식적 방법으로 검증 했다.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.410-415
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• 2009

With the implementation of electric power industry reform, the utilities are looking for effective ways to improve the economic efficiency. One area in particular, the equipment maintenance, is being scrutinized for reducing costs while keeping a reasonable level of the reliability in the overall system. Here the conventional RCM requires the tradeoff between the upfront maintenance costs and the potential costs of losing loads. In this paper we describe the issues related to applying so-called the "Reliability-centered Maintenance" (RCM) method in managing electric power distribution equipment. The RCM method is especially useful as it explicitly incorporates the cost-tradeoff of interest, i.e. the upfront maintenance costs and the potential interruption costs, in determining which equipment to be maintained and how often. In comparison, the "Time-based Maintenance" (TBM) method, the traditional method widely used, only takes the lifetime of equipment into consideration. In this paper, the modified Markov model for maintenance is developed. First, the existing Markov model for maintenance is explained and analyzed about transformer and circuit breaker, so on. Second, developed model is introduced and described. This model has two different points compared with existing model: TVFR and nonlinear customer interruption cost (CIC). That is, normal stage at the middle of bathtub curve has not CFR but the gradual increasing failure rate and the unit cost of CIC is increasing as the interruption time is increasing. The results of case studies represent the optimal maintenance interval to maintain the equipment with minimum costs. A numerical example is presented for illustration purposes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.16-21
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• 2007

A Dual-Path Voltage Multiplier for passive RFID Tags was proposed and fabricated by using a 0.25um CMOS process with additional steps for schottky diodes. The proposed circuit needs only 4 additional diodes, and the area increment compared to conventional one is negligible in multi-stage voltage multipliers. The simulation and measurement results show that the output power capability of proposed multiplier are about two times larger than the conventional half-wave multiplier.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.838-841
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• 2007

In this study, we implemented a $17^*17b$ binary digital multiplier using radix-4 Booth's algorithm. Two stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. To evaluate the circuit, several MPW chips were fabricated using Hynix 0.6-um 3M N-well CMOS technology. Also we proposed an efficient test methodology and did fault simulations. The chip contains 9115 transistors and the core area occupies about $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.394-400
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• 2010

In this paper, We proposed electronic ballast that applys Buck Converter operation principle to Full-Bridge inverter. The proposed ballast consists of an EMI Filter, a full-bridge rectifier, a passive power factor correction (PFC) circuit and a full-bridge inverter. The passive PFC is used and a Full-Bridge inverter operation by two frequency. High Side and Low Side switch was driven by high frequency and low frequency and realized buck Converter's operation. The lamp is driven by Low Frequency square wave to avoid Acoustic Resonance. Also, bulk of inductor is reduced by high frequency switching. Performance of the proposed ballast was validated through computer simulation using Pspice, experimentation and by applying it to an electronic ballast for a prototype 700W MHL.

• Journal of Welding and Joining
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• v.17 no.5
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• pp.61-68
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• 1999

For the last two decades, waveform control techniques have been successively developed and applied for the inverter welding machines resulting in the substantial reduction of spatter generated in CO₂ welding. One of the constituents commonly involved in those techniques is to delay the instant of current increase to some extent after the initiation of short-circuiting. Although this technique has been known to be quite effective in reducing the spatter generation through the suppression of is instantaneous short circuiting, the delay time necessary for minimum spatter has not been clearly understood. In this study, the control system for varying the delay time was constructed so that the spatter generation rates could be measured over a wide range of delay time, 0.29-2.0 msec. As a result of this study, it was demonstrated that spatter generation rate(SGR) sharply decreased at delay time of 0.6 msec and longer accompanied with the change in characteristics of short circuit mode from the instantaneous short-circuiting(ISC) dominant to normal short-circuiting(NSC) dominant. Another feature that have been found in current waveform of over 0.6msec was the creation of current pulse right after the arc reignition stage. Because of this current pulses weld pool oscillated in wave-like fashion and it looks like to play an important role in developing short circuiting between electrode and weld pool.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.690-697
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• 2018

Criticality alarm systems (CASs) are mandatory in nuclear plants for prompt alarm in the event of any criticality incident. False criticality alarms are not desirable as they create a panic environment for radiation workers. The present article describes the design enhancement of the CAS at each stage and provides maximum availability, preventing false criticality alarms. The failure mode and effect analysis are carried out on each element of a CAS. Based on the analysis, additional hardware circuits are developed for early fault detection. Two different methods are developed, one method for channel loop functionality test and another method for dose alarm test using electronic transient pulse. The design enhancement made for the external systems that are integrated with a CAS includes the power supply, criticality evacuation hooter circuit, radiation data acquisition system along with selection of different soft alarm set points, and centralized electronic test facility. The CAS incorporating all improvements are assembled, installed, tested, and validated along with rigorous surveillance procedures in a nuclear plant for a period of 18,000 h.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.