• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.370-371
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• 2011

This paper presents a control algorithm that minimizes the DC-link capacitance by decreasing the capacitor current. The capacitor current can be nullified by a feedback compensation term which is calculated from the power balance in the AC/DC converter. As a result, voltage variation in the DC-link is reduced further, which makes a large reduction in the size of DC-link capacitors which are expensive and have limitations in life time. Simulations are performed with two 80uF DC-link capacitors, which can be replaced by film capacitors.

• 전자공학회논문지B
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• 제31B권12호
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• pp.100-107
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• 1994

This article describes the hardware design scheme of Hamming MAXNET algorithm which is appropriate for binary pattern classification with minimum HD measurement between stimulus vector and storage vector. Circuit integration is profitable to Hamming MAXNET because the structure of hamming network have a few connection nodes over the similar neuro-algorithms. Designed hardware is the two-layered structure composed of hamming network and MAXNET which enable the characteristics of low power consumption and fast operation with biline volgate sensing scheme. Proposed Hamming MAXNET hardware was designed as quantize-level converter for simulation, resulting in the expected binary pattern convergence property.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1578-1581
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• 2009

This work describes a power and area efficient switched-capacitor cyclic DAC for mobile display drivers. The proposed DAC can be simply implemented with one opamp two capacitors and several switches. Furthermore, the op-amp input referred offset is attenuated at the DAC output without additional offset cancellation circuitry. The operation of the cyclic DAC is verified through circuit level simulations.

• Journal of Advanced Marine Engineering and Technology
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• 제38권2호
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• pp.217-224
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• 2014

We have developed the novel device that can extract energy from ocean waves utilizing the heaving motion of a floating mass. The major components of the energy converter are: a floater, a counterweight, a cable, a driving pulley, two idler pulleys, a ratchet, and a generator. The device generates power through the tension force in the cable and the weight difference between the floater and the counterweight. When the system is at static free condition, the tension in the cable is equal to the weight of the counterweight which is minimum. Therefore it is desirable to keep the counterweight lighter than the floater. However, experiments show that during the rise of the water level, the torque generated by weight of the counterweight is insufficient to rotate the driving pulley which causes the cable on the floater side to slack. The proposed application of the tension pulley rectifies these problems by preventing the cable from becoming slack when the water level rises. In this paper, the dynamics model is modified to incorporate the dynamics of the tension pulley. This has been achieved by first writing the dynamical equations for the tension pulley and the energy converter separately and combining them later. This paper investigates numerically the effect of the tension pulley on various physical quantities such as the cable tension, the floater displacement, and the floater velocity. Results obtained indicate that this application is successful in suppressing large fluctuations of the cable tension.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.213-214
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• 2014

This paper compares two instantaneous reactive power definitions in DFIG wind turbine with a back-to-back three-level neutral-point clamped voltage source converter under unbalanced grid conditions. In general, conventional definition of instantaneous reactive power is obtained by taking an imaginary component of complex power. The other definition of instantaneous reactive power can be developed based on a set of voltages lagging the grid input voltages by 90 degree. A complex quantity referred as a quadrature complex power is defined. Proposed definition of instantaneous reactive power is derived by taking a real component of quadrature complex power. The characteristics of two instantaneous reactive power definitions are compared using the ripple-free stator active power control algorithm in DFIG. Instantaneous reactive power definition based on quadrature complex power has a simpler current reference calculation control block. Ripple of instantaneous active and reactive power has the same magnitude unlike in conventional definition under grid unbalance. Comparison results of two instantaneous reactive power definitions are verified through simulation.

• 전기전자학회논문지
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• 제12권3호
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• pp.176-183
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• 2008

본 논문에서는 DTMOS(Dynamic Threshold voltage MOSFET) 스위칭 소자를 사용한 고 효율 전원 제어 장치 (PMIC)를 제안하였다. 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하여 PMIC를 구현하였으며, 낮은 온 저항을 갖는 DTMOS를 설계하여 도통 손실을 감소시켰다. 벅 컨버터(Buck converter) 제어 회로는 PWM 제어회로로 되어 있으며, 삼각파 발생기(Saw-tooth generator), 밴드갭기준 전압 회로(Band-gap reference circuit), 오차 증폭기(Error amplifier), 비교기(Comparator circuit)가 하나의 블록으로 구성되어 있다. 삼각파 발생기는 그라운드부터 전원 전압(Vdd:3.3V)까지 출력 진폭 범위를 갖는 1.2MHz 발진 주파수를 가지며, 비교기는 2단 연산 증폭기로 설계되었다. 그리고 오차 증폭기는 70dB의 DC gain과 $64^{\circ}$ 위상 여유를 갖도록 설계하였다. Voltage-mode PWM 제어 회로와 낮은 온 저항을 스위칭 소자로 사용하여 구현한 DC-DC converter는 100mA 출력 전류에서 95%의 효율을 구현하였으며, 1mA이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

• 전자공학회논문지SC
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• 제37권6호
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• pp.64-72
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• 2000

본 논문은 고속전철 보조전원장치에 사용되는 2대의 PWM 컨버터 병렬운전에 관하여 다루고 있다. 고역률을 이루고 변압기 1차측 전류 고조파 성분을 줄이기 위하여 3레벨 PWM 스위칭 방법에 의해 제어되는 AC/DC PWM 컨버터의 병렬운전을 제안하였다. 본 논문에서는 변압기의 결합효과를 제거하기 위한 제어기법과 컨버터 2대 사이의 위상전이기법 및 전원과 제어기를 동기화하기 위한 영점 검출방식을 나타내었다. TMS320C31 마이크로 프로세서와 10［kVA] PWM 컨버터로 구성된 축소시스템에 의한 실험 결과들은 제안된 알고리즘의 타당성을 보여주고 있다.

• 전력전자학회논문지
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• 제20권3호
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• 전기전자학회논문지
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• 제24권1호
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• pp.19-24
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• 2020

본 논문은 FPGA의 언어 중 하나인 Verilog HDL을 사용한 100 kHz 스위칭의 3-레벨, 2-레벨 SVPWM 기법을 구현에 대한 것이다. 인버터에 주로 사용되는 IGBT소자의 경우 주로 20 kHz 근방에서 스위칭 주파수를 가진다. 최근 차세대 전력 반도체 소자의 연구 개발로 100 kHz 이상의 스위칭을 구현하여 전력변환기를 소형화하고, 고조파의 주입에 따른 여러 가지 새로운 알고리즘의 적용이 가능하게 되었다. IGBT를 이용하는 기존의 시스템에서는 DSP를 이용한 제어가 이루어지는 것이 통상적이나, 100 kHz 스위칭을 위한 제어기 구성으로는 FPGA를 이용한 제어기의 적용이 요구된다. 따라서 본 논문에서는 FPGA를 사용하여 2-레벨 인버터와 3-레벨 인버터에 적용되는 SVPWM의 이론과 FPGA 구현에 대하여 설명하고 SVPWM의 출력 파형을 통해 구현 성능을 확인한다. 한편, 본 논문에서는 3-레벨 인버터에서 SVPWM 구현 시 기존의 방식에서 반송파 2개를 사용하는 방법을 대신하여 반송파 1개만을 사용하는 기법으로 3-레벨 SVPWM을 구현한다.