• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.15-20
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• 2015

Bit patterned media (BPM) is a high capacity storage system and has attracted a great deal of attention as next generation data storage. When BPM is made with high density, the space between the islands narrows, because BPM records one bit in an island. For this reason, BPM has inter-symbol interference in all directions, unlike in current storage systems where it is in only one direction. In this paper, we propose an equation for compensating two-dimensional ISI. We conduct experiments on track misregistration. When using the proposed inter-symbol interference preprocessing, the BER performance is improved, regardless of the amount of track misregistration.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.3-8
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• 2013

Bit patterned media (BPM) storage is one of the promising technologies to overcome the limitations of the conventional magnetic recording. However, there are some problems in a high areal density BPM storage, inter-track interference, inter-symbol interference and noise which are severely degrading performance of the system with reducing the bit error rate. In this paper, we present a simple iterative two-dimensional equalizer based on the contraction mapping theorem to mitigate these adverse effects. Furthermore, we examine that the channel characteristics of the proposed two-dimensional equalizer satisfies the convergence conditions. In the simulation we demonstrate the bit separation characteristics of the one-dimensional equalizer and the two-dimensional equalizer and evaluate the BER performance of the proposed equalizer comparing with the conventional equalizers. According to the results of experiments, the proposed equalizer is an promising equalizer with maintaining proper complexity for a high areal density BPM storage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.3
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• pp.121-126
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• 2014

Demand of the data storage becomes more and more growing. This requests the next generation of storage devices to have the dominated storage capability associated with superfast read/write rate. Holographic data storage (HDS) is investigated for a long time and is considered to be a candidate for the future storage system. However, it has two-dimensional intersymbol interference that conventional one-dimensional detection solutions have not yet handled strictly because of the complexity level of system as well as the cost. We propose a new scheme that combines iterative soft output Viterbi algorithm with noise filter for improving the bit error rate performance of HDS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.739-743
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• 2013

In this paper, a two-dimensional (2-D) channel code for magnetic patterned media is proposed. Patterned media records an information bit on a magnetized dot. Since the space between adjacent tracks is narrow in order to increase the storage density, inter-track interference (ITI) and inter-symbol interference (ISI) can be problems. The amplitude of a bit signal can be corrupted by the 2-D ISI. The signal of the bit surrounded by the same value can be especially destructive, i.e. when its value is the same as the values of the eight surrounding bits. The proposed modulation coding scheme improves the decoding performance of patterned media by preventing this worst case and provides a better code rate than conventional channel codes.

• ETRI Journal
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• v.29 no.5
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• pp.691-693
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• 2007

Existing methods to process continuous range queries are not scalable. In particular, as the number of continuous range queries on a large number of moving objects becomes larger, their performance degrades significantly. We propose a novel query indexing method called the projected attribute bit (PAB)-based query index. We project a two-dimensional continuous range query on each axis to get two one-dimensional bit lists. Since the queries are transformed to bit lists and query evaluation is performed by bit operations, the storage cost of indexing and query evaluation time are reduced significantly. Through various experiments, we show that our method outperforms the containment-encoded squares-based indexing method, which is one of the most recently proposed methods.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.148-152
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• 2004

The direct lateral profile and retention characteristics of locally trapped-charges in the nitride layer of the two-bit polysilicon-oxide-nitride-oxide-silicon (SONOS) memory are investigated by using the charge pumping method. After charges injection at the drain junction region, the lateral diffusion of trapped charges as a function of retention time is directly shown by the results of the local threshold voltage and the trapped-charges quantities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1037-1043
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• 2006

In this paper, we introduce a two-dimensional modulation code for holographic data storage systems(HDSS), which is a candidate for the next generation data storage system. The two-dimensional(2D) intersymbol interference(ISI) induces higher bit error rate(BER). The balanced number of zeros(dark) and ones(light) in each page reduces inter-page interference(IPI). The code rate is 519. Although the proposed code has higher code rate than other 2D code with rate 4/9, the BER performances of two codes are similar.